Editorial

Overcoming Obstacles in Designing with Reusable Cores

The million-gate system-on-a-chip IC will require the incorporation of library elements to be practical.

  by Jonah McLeod

Driven by the insatiable demand from the personal computer and communications markets, the semiconductor industry is changing at a rapid pace. Designers are having to design increasingly more complex circuits in a decreasing amount of time.

"Before, it took typically nine months to design a chip; now, it has to be done in three months," says Sanjay Rekhi, senior CAD engineer at Cypress Southeast Design Center (Starkville, MI). "Minimizing the design effort is critical if these tight time schedules are to be met. We're looking at solutions to help achieve this goal."

One solution is reusable cores: MPEG decompression engines, PCI bus controllers, specialized DSPs, etc. Combining several complex cores using gates and standard cells is much more manageable than designing a million-gate device one gate at a time.

However, one problem facing the widespread commercial adoption of reusable cores is providing protection of the owners' intellectual property. Another difficulty is coming up with a common medium of exchange for transporting the core from vendors to designers and from designers to fabs in order to build the resulting design.

One solution being promoted is Verilog and VHDL models of the cores. Accepting this solution, the designer must create an original layout for each core along with the standard logic he has designed to tie the cores together. In a million-gate design, that's a lot of layout.

A more attractive solution is to use the existing optimized layout for each core. This solution contains the final layout task to only the newly created logic and interconnections between the standard cells. In this scenario, the designer purchases behavioral models along with GDSII layout files of each core.

PC companies eager to reduce motherboard real estate by combining several chips onto a system-on-a-chip are asking companies such as Chips & Technologies Inc. (San Jose, CA) and other fabless semiconductor companies to provide their PC chip sets as cores.

The PC company buying a core from Chips & Technologies and another from Cirrus Logic Inc. (Fremont, CA) receives layout that has been optimized for different fab lines. Furthermore, the PC company will create the final chip on yet another fab.

For reusable cores to be practical, each core vendor must create a layout to a set of virtual design rules. Vendor cores will be optimized for this rule set. Thus, a core can be fabricated on any fab that accepts the virtual design rules.

Library companies are promoting themselves as suppliers of these virtual design rules. Compass Design Automation Inc. (San Jose, CA) offers its Optimum Silicon (OS) library. Aspec Technology Inc. (Sunnyvale, CA) has QuickPort to achieve the same result.

However, for the solution to succeed, library companies must convince vendors to create layout for their cores using the virtual library. In addition, library vendors must ensure their resulting core layout runs on widely used fabs.

Finally, these libraries must achieve gate density and performance within 10 percent of a design that would otherwise be created with the fab's own design rules. Library companies now claim a difference smaller than 10 percent, but this is unlikely, considering the range of variation in fabs.

Jonah McLeod is editor-in-chief of Integrated System Design.

integrated system design  June 1996