Editorial

Can the Gate Array Market Be Saved? One vendor's proposal to stem the tide away from gate arrays toward standard cells. by Jonah McLeod

A marked change in ASIC design is occurring in which designs once implemented in gate arrays are now going into standard cells. Escalating cost and longer time-to-market are driving designers away from gate arrays. However, Chip Express Corp. (Santa Clara, CA) hopes to reverse the trend compelling this shift in the market.

The value in gate arrays over standard cells had been that the former provided faster time-to-market at a lower non-recurring engineering cost than the latter. For this, designers paid a premium in a slightly larger die size for a gate array.

With the advent of deep submicron process technologies, the value changes. Gate arrays in a 0.35-µm process have three metal layers, requiring six masks. Previously, gate arrays had two layers, requiring four masks.

These masks previously cost $1,500 and could be turned around in a day. For deep submicron processes, the masks can cost from $4,500 to $8,000 and demand several days for turnaround. In general, gate arrays' time-to-market advantage over standard cells is diminishing.

Changes in IC fabrication are largely responsible for this drop in time-to-market. Semiconductor manufacturers have invested R&D into interconnect by adding up to six layers and upgrading via material with tungsten.

Similarly, IC designers are concentrating their greatest efforts not in logic design, but in eliminating timing errors in interconnect.

All the negatives notwithstanding, Zvi Or-Bach, president and CEO at Chip Express, believes that designers will return to gate arrays if the devices provide faster time-to-market. He cites the continuing success of FPGAs as proof.

If he can create a gate array with an FPGAs' benefits, Or-Bach believes that he can revitalize the dwindling market. His solution lies in Chip Express's rapid prototyping capability, where lasers create interconnect from a netlist overnight.

The advantage of using an FPGA is that the designer does not have to achieve 100-percent correctness before implementing a design in silicon. The turnaround time for a gate array design iteration demanded this certainty. At deep submicron process rules, designers are spending exorbitant amounts of time simulating and verifying timing on a design before going to first silicon.

In their paper titled "Strategies for Fast Product Innovation," Behnam N. Tabrizi and Kathleen M. Eisenhardt advocate this change from exhaustive simulation to rapid prototyping.

They conclude this would allow designers to learn faster, rather than work faster. The assumption is that by learning faster, designers can more quickly move their designs to production.

Chip Express has adapt its laser writing capability to configure the interconnect on 0.35-µm arrays. In addition, it is changing its business model. Where before it charged for these early prototypes, it now plans to provide up to three design turns at no cost--as long as the designer agrees to take a certain level of chip production.

Can gate arrays regain their market position by allowing fast design iteration? What do you think? e-mail me at jonah@asic.com.

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  October 1996