Editorial

Managing 100-kgate Designs Demands a New Design Methodology The move to higher gate counts increases tool and analysis complexity, especially in smaller feature-size processes. by Jonah McLeod

Early adoption of next-generation process technology, 0.5-, 0.35-, and even 0.25-µm, is a growing trend in integrated system design. Rapid technology obsolescence and an insatiable consumer demand for more compute power and system features is driving the trend. However, as designs reach 100-kgate densities, logic simulation and synthesis alone are insufficient to create these larger circuits. Designers need a new methodology that will address these larger gate densities.

Increased use of complex cores is one reason why the current methodology does not work. Some blocks, "hard cores," are fully diffused microcontrollers, DSPs, and memory. "Hard cores" are provided as layout that the designer can only place in the design floorplan.

Some are "soft cores," HDL code that can be synthesized along with surrounding logic. Still others are netlists of synthesized gates, "firm cores," that cannot be modified with surrounding logic.

Each of these existing designs has its own timing and test methodology. After stitching these blocks together, the designer no longer has a single-clock synchronous circuit--held to be the ideal of a "clean" design. Instead, the circuit has several different clocks and testing domains which the designer must address.

A new design methodology is needed that involves increased use of design-for-test techniques and timing verification. It also demands a greater amount of design tool automation--use of scripts to automatically direct some specific tool operation.

Increased use of design-for-test is demanded by the variety of different testing methodologies contained in reusable cores. For example, a diffused DRAM core might use built-in-self-test (BIST); a diffused microcontroller or DSP comes with its own set of vendor-supplied test vectors, typically applied via on-chip JTAG; and a soft core might come with vendor-supplied functional vectors that the designer might need to enhance with automatic test program generation (ATPG).

A core not only has its own set of test domains, it also has a unique set of timing domains. Timing verification tools, to ensure that signals move correctly from one domain to another, are a major element of this new design methodology. A static timing analyzer is yet another tool required to cope with large gate-count designs.

Since 100-kgate designs are being fabricated in 0.5-µm processes or smaller, interconnect delay becomes a much greater problem than in larger geometry processes. Another tool increasingly being used for large designs is the floorplanner. Using the tool to produce a preliminary layout of major blocks within a netlist, a designer can extract delays from the long interconnects running between blocks. The designer can then backannotate this data to the logic synthesis tool to achieve a synthesized circuit that more closely resembles the interconnect in the final IC.

In addition, the designer needs to create scripts that direct the operation of each tool in the design flow. This automation will enable the designer to make a change, run simulation, synthesis, static timing analysis, and testability analysis automatically.

This new design methodology can best be described as "construct by correction," instead of "correct by construction."

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  December 1996