Vendor makes suggestions for product evaluations.

FEEDBACK

In your September issue there is an article about optimizing layout of high-speed digital PCBs [by Heinz Jakibczuk].

It seems that most of the time-savings comes from the layout cycle, since additional simulation saves the "back and forth" between engineering and layout. A good DFM layout should not take more than two to three weeks on the motherboard and less on the processor, so I'm not sure where he got all the time savings...unless they have a poor layout group to start with, and the fab cycle is bizarre. There is no such thing in the U.S.A. as a four to six week turn on a prototype fab. We turn prototypes in four to six days! or two weeks with no premium at all. We have done the layout and fab on exactly this kind of board in a total of two weeks. The engineers took two to three weeks to get the schematic to us prior to layout. And it booted within a couple of days. In fact, that is normally what we see, working with customers such as Compaq and Ross Technologies.

Darrell Vaughn
Automated Circuit Design

Larry Waller's column, "Shrink-Wrap PLD Design Tools?," in the September 1996 issue, struck a dissonant cord with two Silicon Valley companies. Synplicity Inc. (Mountain View, CA) and Cypress Semiconductor Corp. (San Jose, CA) feel their contributions to this newly embraced model had been overlooked in the column.

Dear Editor,

I'd like to inform you that Synplicity was overlooked by Larry Waller when writing "Shrink-Wrap PLD Design Tools" in the September 1996 issue.

As a producer of EDA tools, Synplicity has made a significant contribution to the paradigm of "shrink-wrap" or easy-to-use PLD design tools in the area of logic synthesis products with "Synplify." Synplify was the first truly "push button" synthesis tool for FPGAs and CPLDs. You just click the Run button, and in minutes, or even seconds sometimes, Synplify synthesizes your design to a netlist ready for place and route. Synplify's blazingly fast run times contribute to the ease-of-use because it makes iterations quick and easy, and enables large synthesis runs. Synplify's integrated editor highlights user-errors directly in your code for fast debug. Synplify also seamlessly fits into all vendor and EDA design environments through the standard interfaces of Verilog and VHDL.

Synplicity has proven that with the high level of cooperation it has received from the FPGA and CPLD vendors, it has been able to put together a product that has big advantages for users--one that allows users to stay vendor independent, and easily synthesize with high-quality results to the vendor of choice, including Actel, Altera, Cypress, Lucent, QuickLogic, and Xilinx .

Kent Jaeger
Vice president of marketing
Synplicity Inc.

Dear Editor,

We wanted to point out that there was no mention of Cypress in Larry Waller's September column entitled "Shrink-Wrap PLD Design Tools?."

Cypress is the leader in this area, having pioneered low-cost VHDL software tools for programmable logic. Our Warp2 software now boasts more than 13,000 installed seats. We have trained more than 3,000 engineers in 23 countries to use VHDL effectively for PLD design. We even wrote a college text book, published by Addison Wesley, entitled "VHDL for Programmable Logic."

We began development of our software in 1989. Today, after investing over $20 million, we sell Warp2 for only $99.00, a price that includes device-specific synthesis with user-selectable optimization for both speed and area, VHDL and Verilog simulation timing modes, full on-line documentation and tutorials, and free customer support. Only Cypress can offer this level of support at such a low price because we have written our own synthesis tool.

Your readers certainly deserve a more thorough examination of subjects such as this in the future.

Larry Jordon
Vice president of marketing
Cypress Semiconductor Corp.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  October 1996