Programmable Notes

Programmables Replacing Gate Arrays? Not Quite Yet, but Soon The price-performance-density of FPGAs is approaching the low end gate arrays. by Larry Waller

For the past three years, faster, denser PLDs have been expected to replace low-density (fewer than 20 kgates) masked gate arrays.

Supporting this scenario is the PLD's reprogrammability. It provides design flexibility and rapid prototyping, paying off in shorter time-to-market for equipment. Proponents predicted former and present gate array users would rally to these benefits as PLD prices dropped at a 30 percent annual clip. The price decline brings them more or less into line with arrays.

Most industry officials agree with the following comment from Chris Henry, director of marketing for AMD Corp.'s programmable operation (San Jose, CA): "at 3x, the floodgates open and programmables grow like crazy. That's the number we look at."

Trouble is, despite numerous programmable products launched over the past several years, and despite prices dropping as predicted, this 3x target still remains elusive. In fact, according to "Status 1996," the yearly report on the IC industry, compiled by market researcher Integrated Circuit Engineering (ICE) of Scottsdale, AZ, in 1995, "the price-per-gate for the PLD device was 6x the price of a similar density CMOS gate array." This represents a substantial improvement from 1993 when the ratio stood at 15:1, the report says.

Key to developing this replacement business, is having a strong product line of competing density, speed, and price. Introductions of these were slow in coming early-on but picked up noticeably last year. Leading the pack from the beginning was the XC4000 FPGA family from Xilinx Corp. (San Jose, CA). More than their competitors, they have aggressively gone after this business. Subsequently, a stream of improved XC4000 FPGAs with smaller feature sizes have rolled out from the company, most recently the XC4000EX, unveiled in January. These newest devices have logic densities ranging up to 125k usable gates. They are the most ambitious yet, since they target a range above the low-density gate array level. Processed on 0.35µm technology, the devices achieve system performance up to 66MHz. They are "the most powerful solution (for the gate array replacement market), addressing 80-plus percent of the 1996 ASIC starts," claims Chuck Fox, vice-president for product marketing. The company says all but the largest devices will be available this year.

Other FPGA suppliers, such as Actel Corp. (Sunnyvale, CA) and Atmel Corp. (San Jose, CA), also have new product lines that address these replacement sockets. Actel , new 0.5µm 32DX FPGA family, in particular, is expected to attract customers with its A32200DX--a 20k device that started shipping in January. Atmel is in the replacement hunt with its new AT6010, also in the 20 kgate range. For the last several years, AT&T Microelectronics (Allentown, PA) has been successfully touting its ORCA FPGA line as alternatives to gate arrays.

Despite being dismissed by some FPGA firms as only "upgrades of PALs," CPLDs are also deeply involved in this business. Altera Corp.'s (San Jose, CA) SRAM-based FLEX 8000 family, whose higher densities of up to 50 kgates are shipping, is picking up sockets that previously would have been filled by gate arrays, the company reports. AMD, which already had its hands full launching higher density CMOS products in March introduced a MACH 6 CPLD line that goes after gate array replacement with densities upwards of 20k.

The ICE 1996 Status report analyzes how the replacement business actually has unfolded in the past three years. In particular, it uncovers interesting data about the pricing competition between gate arrays and PLDs. Using comparable devices at the 10k usable gate density level, the PLD costs $39 and the gate array, $6.50. ICE found that in 1995, PLDs were more cost effective at volumes below 1,396 units. Above that, the high, fixed cost of gate arrays associated with NRE charges could be amortized to the point where PLDs lost their advantage, according to ICE research and calculations.

The Scottsdale market researcher says even though "gate array devices look favorable at all but the lowest volume levels," PLDs still have experienced a replacement sales surge. Why? Time-to-market is the reason designers previously wedded to gate arrays are turning to programmable devices.

ICE says this time-to-market factor now overrides other considerations. Product life cycles of six months to a year don't leave designers room for sticking with gate arrays where lead times recently have stretched to as long as 30 weeks for prototypes, notes Actel's director of marketing, Robert Nalesknik.

In addition, these potential programmable users are getting caught up in the excitement of FPGA growth. In the view of Atmel's director of FPGA marketing, Joel Rosenberg, "it's the dynamism of FPGAs that is doing it (spearheading gate array replacement)." Instead of using PLDs to prototype, then switching to gate arrays for volume, as theory holds, "the FPGA benefits are so pervasive people like to stay with them no matter what."

Also working to the programmable side's benefit has been the decision by gate array vendors to concentrate on higher density devices. ICE points out this GA segment has been booming since 1992. These vendors have become so selective that they often turn down low-density business. Mostly, low-density gate arrays are done for only the best customers as, more or less, a favor. In addition, Japanese firms, the largest gate array suppliers, now focus more on profit than volume production--the opposite of their previous philosophy, notes Xilinx's chairman, Bernie Vonderschmitt. "This (low density) is not good business for the Japanese," he says. This bodes well for programmable dominating low-density designs by decade's end.

Although programmables are penetrating steadily deeper into gate array territory, exactly where they stand today in sales volume is not clear. "Nobody's really keeping close track of this market," observes Actel's Nalesnik. ICE puts the low-density gate array niche at about $1.1 billion in 1995. Even Xilinx had only a fraction of that total with all the success of its XC4000 family. Chuck Fox of Xilinx predicts some $250 million XC4000 sales this year, largely from replacement. But even with a stronger push from the other firms, there is still a long way to go before programmables dominate.

Indeed, some observers see little evidence of replacement in product areas they watch closely. Will Strauss of Forward Concepts (Tempe, AZ), whose specialty is DSP chips and equipment, is one. "I'm told they (programmables) are replacing gate arrays in the DSP area, but they must see something I don't. Maybe later, but not yet," he notes.

Market analyst Ronnie Rohletter of Pace Technologies (Scottsdale, AZ) agrees, pointing out that it takes a while before the "interesting product announcements of the past year really get moving." But she expects the higher density devices to attract customers at a faster clip through the '90s. In the meantime, "it's a wait and see" attitude for her.

Xilinx's Fox has no doubts about what will happen when the crossover pricing hits 2x in 1999: "between 2 and 3x, gate arrays will go to zero."

Larry Waller is a contributing editor for Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  May 1996