Programmable Notes

Shrink-Wrap PLD Design Tools? PLD design tools entering the era of shrink-wrapped software could support HDL for the mass market. by Larry Waller

Who can best supply PLD design tools has been a critical issue for well over a decade. The first PLDs could only be designed with the device supplier's proprietary, in-house tools, which locked users into using a single device architecture. By the early 1990s, the third-party EDA outfits saw the opportunity and got deeply involved, seeking to deliver a more universal-type of design "platform" solution in which users could have more architectural choices by plugging in specific packages for different devices.

However, this newer approach never quite worked as expected, as alliances between big EDA firms, smaller software developers, and silicon companies caused confusion over which supplier was on what side. More importantly, and further changing the design landscape, was the fairly current spread of HDL design techniques. HDLs afford numerous advantages in device density management--not to mention producing a standard code that is highly transportable across architectures.

If these chronologically overlapping trends were not confusing enough, consider how the economics of software development and support fits into the big picture. It is well recognized that coming up with good software tools, from the basic place and route function on up the feature scale, is an expensive proposition for anyone--at least equivalent to the costs of R&D for devices. The costs of development and support favor the Silicon vendors who, unlike their EDA competitors, can absorb the costs with device sales.

Furthermore, the newest users of programmable logic, who constitute a major growth segment, have grown resistant to how much they are willing to pay for entry software. Generally, about $5,000 is the break-point--above that, they get balky. Although, as designers learn the PLD ropes, demanding more features and performance, the cost levels of the tools start to rise.

Now, the software scene is once again undergoing change, as important developments in past months are signaling that a powerful trend is well underway. It gives promise of helping to sort out always confusing design questions for both suppliers and users alike.

The premier happening is the announcement by Xilinx Inc. (San Jose, CA) of its Foundation Series, an integrated set of low-cost, Windows and HDL-based design tools. With new software tools now introduced and others slated for coming months, access will be provided to such industry standard HDL features as synthesis, schematic entry, and gate-level simulation, along with Xilinx' own tools for place and route.

Not only does the entry-level tool-set have these features at low initial prices, $495 to $5,995, the FPGA leader has supplied a customary marketing twist. "Shrink-wrapped" software is likely to stick as the essence of this software trend, whose main attraction already seems to be ease of use.

In the interest of fairness, however, it should be noted that Xilinx is by no means the first PLD supplier to offer a low-cost software set with a host of similar design features. QuickLogic Corp. (Santa Clara, CA), has been marketing a low-cost, Windows-based package and, last June, announced the newest version, QuickWorks 6.0. It has similar features to the Xilinx Standard VHDL product, at only $3,000. "We're the early evangelists of Windows tools," claims Ed Smith, director of marketing.

Nor do these two companies have this low-cost PLD software design tools field to themselves. Both Altera Corp. (San Jose, CA) and Actel Corp. (Sunnyvale, CA) have existing entry level tool sets that are doing very well in acceptance, the firms report. But they are reconciled to the attention Xilinx is now getting, despite Xilinx being what a competitor calls "reactive" with its shrink-wrapped offering. Xilinx's dominant FPGA market position serves to focus increased scrutiny of whatever it undertakes.

For its part, Xilinx went emphatically to its low-cost Foundation Series because "there was no HDL tools in sight from the EDA community that hit the right price points (for the mass market)," according to Kenn Perry, director of software marketing. The key to helping entry users is integrating into a common design management environment what he calls the "complete solution," or all the needed tools from design entry through implementation and verification.

Since these are largely VHDL-based, often presenting a challenge to neophyte designers, a tutorial called "HDL Wizard" eases the tasks with a number of aids and prompts. This feature that teaches users in easy steps is regarded as possibly the most notable contribution of the Shrink-wrapped trend, many observers say. QuickLogic in its new QuickWorks 6.0 takes the idea even further with an integrated multimedia training course that allows users to learn VHDL interactively with hands-on exercises.

Xilinx' concedes, and competitors point out, that its role with the Foundation tools is chiefly as a systems integrator, bringing together software mostly from third-party vendors. For example, Aldec Inc. (Henderson, NV) supplied gate simulation and the HDL editor, among other functions; VHDL synthesis came from Metamor Software Inc. (Beaverton, OR) and the Able compiler was done by Synario Design Automation Inc. (Redmond, WA). Xilinx says that more contributions will be forthcoming in future months from the in-house expertise stemming from the NeoCad (Boulder, CO) acquisition of several years ago. Perry himself was previously a NeoCad official.

As for the approach of supplying company-specific software functions to run on various EDA industry platforms, these don't work out for the mass user market at the lower density levels, in the opinion of most PLD firms. For more sophisticated designers who work with larger devices above the 20 kgate range, it is still evidently another story, however, as Xilinx will continue its OEM relationship with such EDA firms as Viewlogic Systems Inc. (Marlboro, MA).

Observers who appreciate new twists is the field, such as industry consultant Rita Glover, president of EDA Today (Phoenix, AZ), can't find enough compliments for the emergence of Shrink-Wrapped-type tools. The different parts of Xilinx' Foundation, in particular, "work so well together," she notes. In fact, she sees this overall development "representing a whole new philosophy and mentality" in integrating third-party tools into a more open design system architecture. Producing a standard HDL source code itself is a "big step ahead in not locking users into specific devices."

This technology-independent aspect of the new software tools is undoubtedly an important selling point, but one that remains to be demonstrated in practice. Altera's Bob Beachler counts himself among the skeptics on this score, largely because it seems to imply that Xilinx tools could somehow produce design data that could then be instrumental to evaluate and perhaps buy competitive devices. The Altera director of communications and strategic planning says "I guarantee that (anyone) will not be able to buy software from Xilinx that supports Altera devices."

Opinions from Altera and Actel on the Xilinx software in fact give clear evidence that the keen competition between all these rivals is finding a new arena. Beachler criticizes the Foundation tools as nothing very innovative, but merely "stitching together existing solutions." By contrast, Altera has developed most of its design tools internally. Actel's Robert Nalesnik, director of product marketing, notes his firm has had a $3,500 VHDL tool set with many of the current features for two years and devoted much effort to make them "work together in a seamless fashion, with a smooth design flow path." Xilinx could require much more time to pull off an equal feat, he notes.

Surprisingly for this sharp-tongued marketing peer group, QuickLogic's Smith is magnanimous about the Xilinx development. He regards it as validation of the low-cost, Windows-based design pioneered by his firm. Therefore, he praises Xilinx in joining the move to industry standards, "benefiting users previously trapped in costly proprietary tool sets." Moreover, he regards the Xilinx move as important in confirming a trend spotted by QuickLogic and others. "The battleground for FPGA sockets is rapidly shifting to software," he says. "It is now a framework of industry standard HDL design languages working closely with silicon to generate high-performance implementations."

Larry Waller is a contributing editor for Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  September 1996