Programmable Logic

Implementing PCI in an FPGA

Flexibility and predictability are key elements in choosing an FPGA for a PCI interface.

by Mike Dini

Peripheral component interconnect (PCI) has become the standard of choice for implementing bus functions across heterogeneous computing environments. This complex standard bus covers a variety of functions, including video, network and SCSI interfaces for PCs, portable devices, and communications products.

When a European manufacturer of large format filmmaking equipment decided to upgrade their controller interface, PCI was the logical choice. The manufacturer's equipment already afforded its users the advantages of speed and pixel accuracy, but to give the maximum flexibility possible, the manufacturer changed its controller interface so that the equipment could be interfaced to a broad range of host computer environments. This change would enable customers to make trade-off choices between hardware platforms, software performance, and costs.

Figure 1. QuickLogic's QL24x32B FPGA is part of the pASIC 1 family of parts. It has 8k usable gates, 786 logic cells, 188 I/O pins, and incorporates the company's proprietary ViaLink metal-to-metal antifuse technology.

However, this modification also over-stretched the manufacturer's four-person design team. They could not learn PCI design and Verilog fast enough to meet the required schedule. Therefore, the manufacturer called in the Dini Group (San Diego, CA) to fill in the design gaps. The design process took approximately seven months.

The challenges of implementing PCI in FPGAs The manufacturer's film making equipment costs $250,000 per system, with annual quantities sold in the hundreds, so gate arrays were not a cost-effective choice. Therefore, the manufacturer chose to implement the interface using FPGAs.

There are two major challenges in using FPGAs for PCI-based applications. First, because of the basic requirements of PCI, many resources are needed to implement the requirements. Second, these resources have to run at a fairly high speed--33 MHz. PCI requires a configuration memory in every design. This configuration memory is 16 long words and contains the necessary elements for plug and play, such as device and vendor I/Os, base address registers, and other configuration variables.

Low logic density requirements such as slave-mode PCI can use a 255 flip-flop CPLD. The timing specifications, however, require the fastest device offered. For the higher-end PCI applications, notably Master Mode transmit and receive in burst mode, a CPLD has insufficient flop-flops.

Figure 2. The block diagram for the PCI controller shows the connections to the other functional blocks in the interface.

The design particulars The manufacturer's PCI controller interface required a Master Mode receive-only interface. In addition, a variety of other registers were required to control the optical link. Further, the controller interface had to account for the varying burst cache sizes of the different platforms.

To implement the PCI controller interface, the manufacturer selected the QL24x32B FPGA and a PCI design kit from QuickLogic Inc. of Santa Clara, CA (See Figure 1).

This particular design was 50 percent schematic and 50 percent Verilog. Schematic entry was used in the areas where the design needed to be tweaked for speed. The part was hand-designed at the architecture level, and then those elements of the design that didn't require as much speed were done at the HDL level for efficiency gains.

Design modifications Several major customizations had to be made to the PCI Design Kit for the application. Modifications to the PCI design included stripping out the Master Mode transmit, replacing the interface and the associated circuitry to the ADC 300 with a TAXI controller, and modifying burst counts to accommodate the different burst cache sizes of the targeted host computers. The final design is shown in Figure 2.

The most serious problems centered on getting the TAXI controller to work properly. Asynchronous FIFOs had been used rather than the synchronous FIFOs needed by the PCI's synchronous bus. Issues were also found in the state machine descriptions for the TAXI controller. The chip didn't work correctly during power-up.

The TAXI chip has an 8-bit interface with a FIFO between the TAXI chip and the PCI interface. To get the required bandwidths, the 32 bits from the PCI interface were written into the FIFO. The FIFOs were "filled up," and then the data was multiplexed out 8 bits at a time. Because older style asynchronous FIFOs had been used, the write pulses became very troublesome due to the read and write signal generation. The Dini Group had to go very deep into the Master Mode controller to add an extra wait state during the burst cycles. This was done so enough time could be added for an asynchronous write to the FIFO.

The differences in the chipsets used in Macintoshes, Power PCs, and PCs result in differing cache sizes. The cache size on the Power PC appears to be 16 long words, while it appears to be four or eight on the Intel PC. Two counts are provided in the PCI Kit: the first consists of how much information can be burst, and the second involves how much can be done in the total Master Mode cycle. To accommodate the varying burst rates of the different host computer environments, both of these counts needed to be modified. The manufacturer needed a counter that had a total burst count of 13 bits or 8,000 pixels. The design was modified so that a total of 16 long words were received, rather than eight.

Only the 33-MHz performance challenge remained for this project. The manufacturer was able to get the controller interface to run at 30 MHz. To get the design up to that last 10 percent, the source of the speed problems had to be found and corrected. With FPGA architectures, fan-out can be key because each connection adds a finite amount of capacitance and delay. Also, synthesized designs sometimes generate too many logic levels, increasing delays. In addition to locating the problems, finding the solution can involve other design changes, such as adding additional resources, fanning out more, adding buffers, or resynthesizing for better timing.

Closing thoughts A key factor in getting the PCI controller interface to work centered on fixed-pin rerouting. With fixed pins, there is reliability and predictability in getting performance with a known amount of resource utilization on a particular chip. Because of the amount of routing and interconnect, 100 percent of a QuickLogic part can be filled. The pins can be randomly fixed, and the engineer can still demand the part route while it provides performance. This is not true with equivalent static RAM-based parts. With these other architectures, the part doesn't route; or if it does route, it won't meet the speed requirements. An engineer can spend literally weeks or months having to hand-tune a design through logic-cell-level design and manual interconnect layout because the correct solution can't be easily reached due to limited resources in static RAM-based parts.

Mike Dini is president of the Dini Group (San Diego, CA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  September 1996