PCB Design

Signal Reflection and Pedestal Effect of a Heavily Loaded Net

Termination schemes improve PCB performance

by Mai Vu

High-speed PCB designs benefit from terminations on signal lines. Termination techniques improve noise margins and reduce signal reflections that degrade signal integrity. Designers need to include terminations in their PCB designs for two reasons: (1) to make the design more robust by minimizing reflections and noise due to impedence mismatches, and (2) to minimize the IC output noise sensitivity and match the loads to the IC drive capabilities.

Figure 1. The forward conduction characteristic of the Schottky barrier diode (clamping diode) is used to match the line impedance of the signal path. The variable conduction curve of the diode permits terminating line impedance from 50-150 ohms.

Termination techniques discussed in this article include clamping diodes, resistive terminations, and special wiring rules. Clamping diodes and resistive terminations control line impedances and absorb reflections on the lines. The wiring rules help signals meet the timing and noise margin constraints.

The rules determine the physics of the signal lines. If the lines are sufficiently short, the signal will be rising during the propagation delay of the line, and the reflection will become a part of the rising edge. With longer lines, the rise of the signal will be completed during the propagation delay and reflections will appear as an overshoot and undershoot.

Termination requirements may be expressed in the following rules:

• Termination is NOT required when the two-way total propagation delay is less than the signal rise time: 2Td < tr, where Td is total propagation delay and tr is rise time.
• Termination is required when the two-way total propagation delay is greater than or equal to the signal rise-time: 2Td tr.

Designers use line terminations to reduce the reflections on each net. The termination techniques are unique for each application because of different frequency ranges, parts, and timing constraints that each design must meet. Designers should simulate different techniques to determine which fits best in a particular application.

For the best results in a PCB design, position most of the loads as far from the source as possible. This results in the two-thirds rule--to place the first load at about two-thirds of the total line length. Alternatively, the designer can consider this as putting all of the loads in the last third of the line.

Each circuit in a computer is constantly summing up the noise from various noise contributors. The switching noise increases the propagation delays due to output glitching. In many cases, the noise can be traced to poor grounds and poor decoupling at the sources. The following techniques can be used to reduce reflection noise.

Termination techniques for a heavily loaded net Three techniques used for terminating include using clamping diodes, employing series termination, and incorporating parallel termination. Each technique is described in the following pages along with a brief description of the application in which each serves best.

Clamping diodes Observing the two-thirds rule, use clamping diodes as virtual terminations at the beginning of the first load and at the end of the last load. Use dual clamping diodes with one diode connected from output to power supply and the other diode connected from output to ground to clamp both the low and high state. Maximum effectiveness of the diode occurs when it is placed at the end of the line or at the end of a long stub branching off from the main net. Clamping diodes also reduce the negative transients that occur due to discontinuities in the middle of a net.

Figure 2. Series termination is useful for high fan-out and long lines

Advantages of clamping diodes for termination include the following:

• No matched impedance is required.
• No matching termination resistors are required.
• All signal overshoot is effectively clamped to the 1 or 0 logic level.
• All external noise in excess of 1 or 0 logic levels is clamped at the receiving gate or load.
• Ringing problems on a drive line during systems checkout are reduced.
• Does not consume operating power, unlike resistive terminations.
• Unlike a pull-down resistor, clamping diodes do not degrade the VOH levels, resulting in increased noise immunity.
• Clamping diodes do not reduce negative transients, nor do they increase propagation delays on the net in the same way as a series resistor.
• Clamping diodes do not reduce the output drive capability of the driving device in the same manner as a series resistor.
• Clamping diodes do not produce an RC time constant on the net, unlike a series resistor in combination with the inherent load capacitance of the transmission line.

The forward conduction characteristic of the Schottky barrier diode, the clamping diode shown in Figure 1 , matches the line impedance of the signal path. The variable conduction curve of the diode permits terminating line impedance from 50 to 150.

Series termination Use series termination with the split, branch-off concept to achieve a faster timing specification, compared to the clamping diode. The series termination can be seen in the following diagram. The value of the resistor is determined by the equation Rs+Ro=Zo, where Rs is the series resistor, Ro is the circuit output impedance, and Zo is the impedance of the line (see Figure 2 ).

The advantage of series termination is it requires less overall power. Since all the reflection is absorbed at the source, reflection at the receiving gate does not limit the number of lumped loads that can be placed at the end of the series terminated line. A series damping resistor limits the undershoot. It also limits the overshoot and ringing. Series damping can be used to extend lines to any length while limiting overshoot to typically 35 percent and undershoot to typically 12 percent. The disadvantage of series termination is slower propagation delay and reduced DC noise margin.

Parallel termination Four possible parallel terminations exist. However, compared to other types of termination, they do not all work well with a heavily loaded net: ³

Pull up resistor This configuration will consume current from Vcc when the output is low.

Pull down resistor This configuration will consume current from Vcc when the output is high.

Dual termination resistor or split resistors The configuration will consume half of the current from the output stage of case 1 and 2. However, it will reduce the noise margins and consume current from Vcc with outputs High or Low. Dual termination resistors on a TRI-STATE bus will set the quiescent line voltage of the bus to one-half.

AC termination This consumes no DC current for either output. If this is used on a TRI-STATE bus, then the quiescent line voltage of the bus can be established at Vcc or Gnd by a high-value, pull-up (down) resistor to the appropriate supply. The capacitor, C, is set at a value equal to 3x the rise time, tr, divided by the line characteristic impedance Zo, (C = 3tr / Zo).

System application For memory line The first choice for a termination should be a clamping diode with the two-thirds rule for the first load. The series termination is the second choice. The timing requirements define which concept should be used. In general, the clamping diode will give a cleaner signal than the series termination, especially when clamping diodes are used at the first and the last loads.

For data line Consider using dual termination resistors first. AC termination can be used as a second option.

For clock line The first choice is a clamping diode with two-thirds rule. AC termination with the two-thirds rule can be used as a second choice.

Guidelines The designer can achieve several performance benefits by adhering to the following guidelines:

• Make sure the line length to the first load of any net is at least equal to two-thirds of the total line length.
• Make the minimum spacing between each load at least 0.5in. to prevent cluster behavior.
• Develop PCB layout rules to ensure minimum distance on all nets. Provide a mechanism for these checks in the design flow to reduce rise-time signal degradation.
• Avoid bundled parallel runs as much as possible between signal layers (Z direction) and between signal lines (X and Y directions) to reduce crosstalk.
• Separate the logic ground from the ground for the high switching current circuitry. All separate grounds should, however, be tied together at the system ground point. By doing so, the ground buses will be at the same potential but current cannot be looped, because they are connected at only one point.

You can maximize the number of loads if several factors are in place. First, the driver must have enough current drive for all the loads and terminations. Second, the IC should have a phase margin of 40 to 45 degrees to support all loading (refer to Bode Plot to calculate the phase margin).5 If the phase margin of the IC is adequate, the part will have much less sensitivity to noise than the IC that has only 4 to 5 degrees of phase margin. Mismatch creates a large amount of reflection noise, so a high phase margin reduces noise sensitivity.

The number of parts needed can be minimized by increased loading on the same net. Also, the waveform shape can be improved and the propagation delay reduced. This can help compensate for the loss of timing and performance due to the degradation in rise time. *

Example 1: For unterminated transmission line 2

Assume 10 loads on the net L = 10in. Length of the net tpd = 0.142ns/in. Propagation delay per inch based on FR4 material Zo = 96 ohms The impedance of the net Cl = 10pF/load Capacitance of each load tr = 3ns Input voltage rise time F240 is the driver with an output resistance high of 23 and a low of 2.5. F373 is a receiver with an input resistance high of 1 Mega and a low of 10k. Propagation delay of the net is Td = tpd x L = 0.142ns/in. x 10in. = 1.420ns. There is no need to terminate the line because 2Td < tr or 2.840ns < 3ns. Propagation delay increases due to loading effect, where total load capacitance is 100pF. Impedance decreases due to loading effect as expressed in equations 1, 2, and 3: (1) Co = Td/Zo= 14.790pF (2) Td' = Td x = 3.960ns (3) Zo' = Zo = 34.5 Parameter for unterminated line 10 inches long Distance to first load Propagation delay to first load tr Final amplitude for first load Output glitch after tr Load distribution 1in. .142ns 3ns 0.866V 4ns Equally distributed loads 5in. .710ns 3ns 1.925V Slight Loads at half of line 6in. .852ns 3ns 2.200V No glitch Loads at two-thirds of line

Example 2: For terminated transmission line 2

Assume 20 loads on the net L = 18in. Length of the net tpd = 0.142ns/in. Propagation delay per inch based on FR4 material Zo = 96 ohms The impedance of the net Cl = 10pF/load Capacitance of each load tr = 3ns Input voltage rise time Dual clamping diodes are used for termination at the end of the net. F240 is the driver with an output resistance high of 23 ohms and a low of 2.500 ohms. F373 is the receiver with an input resistance high of 1 MegaOhm and a low of 10kOhms. Propagation delay of the net is Tpd = 2.560ns. Because 2Td > tr or 5.110ns > 3ns, the terminated maximum line length may be expressed as shown below: L max (in.) = R series () / PC trace resistance ( / in.). R series = maximum voltage drop / I in maximum. Where 4 Maximum voltage drop = maximum allowed DC drop of a particular signal trace. I in maximum = maximum input current to be used on a particular net. PC trace resistance = resistance value of a particular signal trace at a defined line width W. Resistivity of 1oz. copper = 0.67083 mOhm / square. PC trace resistance (W = 7mils) = 0.09583 ohms/ in. PC trace resistance (W = 5mils) = 0.13417 ohms/ in. From equations 1, 2, and 3 in Example 1 , we solve and obtain the following: Distributed load capacitance on the net from equation 1 is Co = 26.670pF. Propagation delay increase due to loading effect from equation 2 is Td' = 7.5ns. Impedance decrease due to loading effect from equation 3 is Zo' = 32.9 where Ctl = 200pF total load capacitance. Parameter for terminated line 18 inches long Distance to first load Propagation delay to first load tr Final amplitude for first load Output glitch after tr Load distribution 0.9in. 0.128ns 3ns 0.740V 8ns Equally distributed loads 10in. 1.420ns 3ns 1.916V Slight glitch Loads at half of line 11in. 1.562ns 3ns 2.045V No glitch Loads at two-thirds of line

References

1. Blood, William Jr. "System Design Hand Book," Motorola Inc.
2. Vu, Mai. "Correlation of SPICE Simulation to Actual Board Results," Harris Computer Systems Corp., Ft. Lauderdale, FL. April 1992.
3. National Semiconductor. "FAST Logic Application Handbook," 1990.
4. Vu, Mai "Noise Margin Reduction due to Series Resistance," Harris Computer Systems Corp., October 1993.
5. Millman and Hakias (Text Book) "Integrated Electronics Analog and Digital Circuits and Systems."

Mai Vu is a lead engineer at Harris Computer Systems Corp. (Ft. Lauderdale, FL).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com

integrated system design  May 1996