PCB Design

Optimizing Layout on High-Speed Digital Printed Circuit Boards

Applying new physical design synthesis tools reduces PCB design cycles by nearly 30 percent.

by Heinz Jakibczuk

Designing a new, high-speed Unix PCB, which included complex ASICs and clock rates in excess of 100 MHz, our team at Siemens Nixdorf Information Systems AG (SNI) in Paderborn, Germany, set out to streamline the electrical design process in an open-systems Unix environment and to produce a PCB that is optimized for manufacturing (see Figure 1). To do this, the team followed three important guidelines for achieving high product quality: (1) establishing a seamless CAD flow, (2) implementing preventive procedures, and (3) optimizing tool integration. These factors are critical to reducing the number of redesigns, and they dramatically increase the chances of producing a correct, first-time design.

Figure 1. With the traditional methodology, it takes 18 to 38 weeks to complete the total design cycle.

Establishing a seamless CAD flow Optimizing designs the first time allows us to shorten development time and to be "just-in-time" to the market with new products. EDAnavigator, from Harris EDA Inc. (Fishers, NY) has helped us to optimize designs by identifying and addressing specific challenges and issues. Within our design process, EDAnavigator allows us to--

• Handle all parametric values with software. These values travel with the design database, eliminating the exchange of rules on paper and re-inspection.

• Improve communications between our engineers and designers.

• Use internal standard rules for manufacturability early in the design process.

• Use electrical rules--such as net classes, component classes, and in-house rules (built-in)--to guide floorplanning and partitioning.

• Employ software-driven in-house rules.

To create a seamless CAD flow, we first established the rules that drive the placement synthesis routine. In our layout design group, we had previously established a spreadsheet system for net class rules. This spreadsheet drives the autorouter that adheres to class-to-class rules, min/max lengths, matching lengths, and layer assignments. High confidence in our autorouter allows us to establish these design rules early in our design cycle and to create a design database that conforms to the established rules.

We have also found that using board and module synthesis produces significant improvements throughout the design process. Rather than going through the usual back-and-forth process between the engineering and layout groups, we can quickly create good placements and consider a variety of what-if scenarios in our own working environment. In the design of the RM400 series (see Figure 3), the design flow progressed through layout without the anticipated CAE to CAD iterations, and after placing components with EDAnavigator the design was routed on the first attempt.

The new design flow, achieved using physical design synthesis tools, resulted in a nearly 30 percent reduction in cycle time (see Figure 2) over the traditional design process (see Figure 1). The concept of physical design synthesis can be applied to all aspects of the physical design process--from partitioning and placement to interconnect. Accomplishing these tasks within a highly integrated environment on our desktops is the key. It allows us to address physical design requirements; thus, the design moves quickly to market without needless design iterations.

Figure 2. With the new methodology, it takes 12 to 24 weeks to complete the total design cycle, achieving a time reduction of nearly 30 percent.

Implementing preventive procedures The goal of preventive procedures is to simulate systems prior to prototype and manufacture. Simulating system features and functions and analyzing critical conditions and stages ensures compliance with the design's specifications. For functional simulation, we create a model of the logic, consisting of standard components--in this example, an R4400 processor from MIPS of Silicon Graphics Inc. (Mountain View, CA), memory, and a bus-controller--based on current models on the market and two ASICs that were described in VHDL.

Electromagnetic compliance (EMC) analysis is designed to achieve radiation compliance (FCC Class B) and eliminate electromagnetic interference. At 83 MHz, the digital design begins to exhibit analog behavior. Critical signals such as clocks are selected and their signal integrity--timing, reflection, and cross-talk behavior--is analyzed. We used EMC Workbench from Incases Engineering GmbH (Paderborn, Germany) for signal integrity analysis, and we used the results of EMC simulation to set up design rules and guidelines for the placement and routing. Following these exact specifications for

Figure 3. SNI's RM400c. The model department server with RISC technology.

length, width, and termination, we were able to perform the EMC simulation and reduce EMC radiation at the precise locations where it was created, thereby enhancing the long-term stability of the product. For example, spikes, which would have reduced the life span of components or resulted in breakdowns due to intermittent errors, were eliminated by modifying placement and ordering termination and, in some cases, by rerouting specific traces. We later confirmed EMC simulation results using measurements from the prototype board.

Siemens Nixdorf builds a Unix box
Siemens Nixdorf has focused on establishing a seamless CAD flow, implementing preventive procedures, and optimizing tool integration. These efforts, supported by the introduction of new tools for physical synthesis and design verification, allowed us to dramatically improve the design process for the new RM400-Model C Unix system that we recently developed. This system was able to boot Unix two weeks after prototype delivery. This is nearly 30 percent faster than previous delivery of similar boards and was achieved with fewer iterations and design cycles. This new system is part of the RM family of scalable servers, which includes systems with uniprocessing technology, symmetrical multiprocessor architectures (SMP), massive parallel multiprocessor architectures (MPP), and combinations of these systems. The RM400-Model C system consists mainly of three PCBs: The main memory using synchronous DRAMs The memory board is equipped with SDRAM components and can have a maximum size of 256 Mbytes. For bus systems with maximum speed of 100 MHz and trace lengths of up to 50 cm, the GTL-logic combines high performance with low power dissipation and high noise immunity. The GTL bus is able to run 83 MHz synchronized to CPU actions. As with the two other boards, synchronized clock-phases were built in during the layout process. The CPU board with second-level cache (SLC) It is equipped with two MIPS R4400/200 microprocessors and 4 Mbytes for each processor (see figure). The MIPS R4400 processor is one of a small number of open RISC processors available on the market. This CPU board provides compatibility with both Unix and Windows NT. The motherboard Two of the ASICs in this system use Ball Grid Array (BGA) packaging technology with 367 pins. BGA technology provides better quality solder processing and, particularly for high pin count designs, results in a smaller contact area, providing better electrical and EMC characteristics.
SNI RM400 & Model C. The motherboard and CPU board with second-level cache.

In addition to EMC simulation, we perform thermal simulation during concept development to predict the air flow and heat transfer on system- and module-level components. Our designers performed detailed thermal analyses using AutoTherm, from Pacific Numerix Corp. (Phoenix, AZ). This analysis allowed us to implement changes and avoid complications from overheating, the primary cause of electronic failures, as well as to make appropriate recommendations for package design and component placement. The results were so good that the final system measurements matched the simulation measurements exactly.

Optimizing tool integration During the design process, we use commercial EDA tools wherever possible. However, the tools must be integrated into the CAD flow--not used as islands in the development process--creating a seamless transfer of data across all phases of the process, from development to production and logistics. Seamless data transfer from one design step to the next avoided data re-entry and the risk of introducing new errors.

Eight years ago, we developed a process and data management tool to control and administer consistent logic and layout data in a common release. Siemens Nixdorf's design process is controlled primarily by this data management tool, with a common storage area on a server, and it is accessed by a wide network. We first create a design work area; the data to be shared is placed into this common area; and then it is controlled by specific attributes and relations from the data management system. At any stage of the design process, the data management tool is able to allow or deny requested actions from the user base.

Design work follows several steps in our system, and it begins with the creation of a project under the data management system. We begin the design with schematic and design entry. In parallel with the schematic entry phase, our engineers simulate the main partitions of the design. After achieving acceptable results from simulation, our engineers then make the decision to complete the design or pass the main parts to our layout engineers.

On the basis of the control mechanisms within the data management system, our electronic engineers and our layout designers are able to work concurrently on the project by a synchronization process inside of one project version. At this point in the design cycle, several synchronization steps can take place depending on the outcome of the ongoing simulation and the completeness of the schematic entry. As part of the data management system, design rules reside in several standard files that can be imported into the design. Currently, we write specific net rules and placement on paper. In the near future, we plan to make these specifications in the schematic entry tool in order to pass this information to all other tools.

After our layout designers complete the layout, we run a final validation to ensure that logic and layout data are consistent and that the correct rules are used. Post process evaluation is then implemented.

Within this environment, we have attempted to use standard interfaces, such as initial graphics exchange specification (IGES) and electronic design interchange format (EDIF), for data exchange between our logic, layout, and mechanical tools. However, we have found that they do not offer many of the functions that we need, such as multi-use of logic, generation of assembly variants, and concurrent design. Therefore, to exchange data, we use proprietary translation software and application-dependent toolboxes to access the databases.

We ensure that the product data are put together consistently in a neutral, EDIF-like format for production and logistics. The different production processes have access to and generate data for PCB production, assembly, test, inspection, and quality assurance. This interface decouples the development and production processes, which means process changes from production will not influence development, and vice versa.

Finally, we use Harris EDA's EDAvalidator in conjunction with our process and data management tool for design verification. This combination ensures that data translated from one EDA tool to another is functionally equivalent to the original, that ECOs are quickly and accurately implemented, and that updates to any CAE, CAD, or bill-of-materials (BOM) databases are accurately reflected in related databases throughout the process. The client/server architecture technology offered by Harris EDA helps us to successfully achieve these results, allowing us to use our existing tools and capabilities and preserve our investments.

Heinz Jakibczuk, is the CAD manager at Siemens Nixdorf Information Systems AG (Paderborn, Germany).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  September 1996