IC Technology

Timing Binds EDA Tools to Foundry

The interplay between design, layout, and process affects system-on-a-chip designs.

by Jonah McLeod

With foundry capability of 0.5-µm and below readily available, IC manufacturers continue to exceed the ability of system designers to use the millions of transistors available on a chip (see "Factors determining deep submicron foundry capability").

As a result, integrated circuit designers must create complete systems-on-a-chip, which contain major blocks of existing intellectual property--microcontrollers, memory, special peripherals--tied together with random logic. Building these complex devices demands a hierarchical design approach between the system architectural-level and detailed gate-level description.

This hierarchical approach emphasizes floorplanning tools early in the design process. These floorplanners use state-of-the-art placement algorithms developed for back-end placement tools. In addition, new routing tools that are better able to accept design constraints, help avoid signal integrity problems created by deep submicron designs. Finally, layout parasitic extraction (LPE) tools are tying these layout tools to the foundry's silicon process.

Winston Jung, product marketing manager at Technology Modeling Associates (Sunnyvale, CA) says this design methodology was fostered by foundries. "Initially the system-level library contained gate-level simulation models," Jung says.

In the olden days, designers created a netlist, and ASIC suppliers performed physical chip layout and fabrication. However, as process technology migrated into the deep submicron regime, circuit speeds in deep submicron processes turned wires into active components. As a result, designers have to perform some of the layout during netlist generation.

In a design hierarchy, each library level abstracts detailed information from the level below (see Figure 1). Moreover, in the deep submicron realm, interconnect parasitic information ties all levels together and binds the system design to the physical silicon. The system description must incorporate physical placement to ensure correct operation.

Floorplanning complex designs Floorplanning is required at the architectural level to achieve a workable layout. The system designer cannot delay floorplannning since the layout not only affects pin placement and net lengths, it also influences logic partitioning. Design systems for deep submicron must account for interconnect parasitics at every level.

During floorplanning, the designer arranges blocks of logic--datapaths, state machines, etc.--to optimize their interaction with neighboring blocks. One objective is to better characterize critical-path timing on long nets.

Simon Napper, vice president of marketing at Epic Design Technology Inc. (Sunnyvale, CA), says "interconnect for long nets is the biggest problem facing designers." Meta Software Inc. (Campbell, CA) estimates that for an average ASIC, interconnect accounts for 30 percent of total chip delay. The estimate assumes the circuit has 0.4-µm transistors, 0.7-µm metal width, and an average metal route length of 3 mm.

Furthermore, Sematech estimates interconnect will determine as much as 80 percent of total delay in an IC implemented in 0.25-µm process rules. Floorplanning a design identifies critical nets. LPE tools estimate the delay each critical net will contain in final layout.

Today, designers floorplan their designs after synthesis. The problem is the design has been converted into gates using statistical wire load models that vary depending on fanout, not length of wire. Back-end tool vendors, such as Cadence, Avant!, and Silicon Valley Research as well as new start-ups such as High Level Design Systems, are developing RTL floorplanners that produce estimates of wire lengths.

Replacing statistical models with estimated wire lengths based on a preliminary RTL layout provides the synthesis tool more accurate timing information. Thus, it produces a gate-level description with fewer timing errors.

The UltraSPARC chip-design employed three different full-chip timing models, says Piyush Patel, logic design manager at Sun Microsystems' Sparc Technology Business (Mountain View, CA). A unit-timing model provided a timing budget for each top-level block. A mixed-timing model predicted gate- and block-level timing, and a flat timing model detailed gate-level timing (see Figure 2).

At 0.5-µm process rules, estimated timing, based on floorplanners that place the top-level blocks in a design hierarchy, is adequate. However, as process rules reach 0.25 µm, Bill Portelli, vice president of marketing at Cooper & Chyan Technology Inc. (Cupertino, CA), believes designers may have to place and route a circuit to eliminate critical-path timing errors.

Once a designer creates a netlist, he or she provides it to back-end place and route to produce a final layout. If the designer has floorplanned his or her design, it is important for the floorplanner to use the same algorithm as the back-end placement tool. Otherwise, the second algorithm will compute differently from the first, thus creating errors.

Suppliers of next-generation placement tools include the two major competitors Avant! and Cadence, as well as new start-ups such as High Level Design Systems and Gambit Automated Design.

State-of-the-art placement algorithms Quadratic placement is the state-of-the-art in placement algorithms, says Stan Sun, principle software engineer at Avant! Corp. (Sunnyvale, CA). It replaces a technology called simulated annealing. The latter operated in the same way a person solves a Rubik's Cube puzzle. With two sides of a cube each a solid color, the player disrupts this order to get all sides to solid colors.

One drawback to the algorithm is that it may achieve a less than optimum placement. With simulated annealing, no solution is an absolute minimum layout since many local minima are possible. Another drawback is the algorithm consumes computing resources exponentially as design size increases.

By contrast, quadratic placement is much faster and its compute time rises linearly with design size increases. Michael Burtstein, president of Gambit Automated Design Inc. (San Jose, CA), says quadratic placement is effective at determining components to place close together. However, it is not as effective in determining which components to place apart to facilitate routing. Determining the latter, Burtstein says, permits optimum routability.

During placement, design hierarchy determines the major blocks to be laid out. One feature of quadratic placement is "soft" blocks. The aspect ratio of these blocks can be adjusted to fit into the area around "hard" (fixed) layout--intellectual property: a microcontroller, peripheral component interface, etc.

In addition, some placement tools can create irregular rectilinear shapes, which can resemble an "L." Rectilinear shapes accommodate such functions as data paths that might contain a floating point section; the floating-point section is wider than the integer arithmetic section, Avant!'s Sun explains.

Another capability in placement tools is the ability to constrain object placement. Sun says

Figure 1. In a design hierarchy, each library level abstracts detailed information from the level below.

that quadratic placement accommodates constraints better than other algorithms. In fact, designers can constrain every path in a netlist without increasing compute time.

Constraining the routing tool Once placement is completed, the router then connects blocks and the circuit components inside of the blocks. However, the problem is not one of running wires between various components. At process rules below 0.5 µm, routing tools must be able to accept many more design constraints than previously demanded. Portelli sites the example of buses. These long lengths of parallel lines invite crosstalk.

Figure 2. Sun used increasingly more accurate timing information as the UltraSPARC design moved closer to a final netlist.

To reduce crosstalk, the tool can increase spacing between wires at the expense of chip area, or it can shield each line. Another solution is to use additional routing layers present in deep submicron processes. Half the bus lines can be in metal 2, while the others are in metal 3. However, at 0.25-µm process rules, crosstalk between metal layers also becomes a consideration.

To accommodate high data transfer rates, bus wires need to be wider than other lines to reduce wire resistance to current flow. Like bus lines, clock wiring needs to be wider to reduce resistance. In addition, clock trees present their own set of problems. A star topology for the clock tree is much more desirable than a daisy chain, for example.

One capability available on the newest routers includes timing-driven detailed routing. Other capabilities include layer control, automatic signal shielding, and differential pair routing. With multiple layers of metal, newer routers can have a different set of rules for each layer as well as unique rules for different areas on the same layer.

After a netlist has been placed and routed in an ASIC design flow, it is annotated with layout timing delays and returned to the system designer. Allen Drew, supervisor of communications layout at Brooktree Corp. (San Diego, CA), explains the iterative process his company uses between back-end layout and front-end design.

The process begins with a layout versus schematic (LVS) check. This verifies that the layout matches the original design specification. Next, a design rule check (DRC) is performed by Cadence's Dracula tool. It executes around 100 checks, Drew explains, to ensure that the layout matches the target foundry's rules.

The tool examines every polygon, spacing between polygons, etc., to ensure compliance. During layout, errors may be introduced by the tools as well as operators, Drew explains. Once the design passes the DRC, it is returned to the system designer for final design verification. The system designer performs system verification to ensure final layout meets timing.

To correct timing faults at this point, the system designer can resize buffers along the failing critical paths to meet timing requirements. A rule of thumb is that if timing is off by 20 percent or less, then buffer resizing is a practical option. Otherwise, the circuit should be laid out again using custom wireload models for more accurate timing estimates.

Tying layout tools and foundry together Tools such as Dracula from Cadence, and Star from Avant! are layout parasitic extraction (LPE) tools. Up to now, LPE tools evaluated polygons in the horizontal plane. They determined the capacitive effects of two adjacent wires, for example. In deep submicron processes, however, the resistance, inductance, and capacitance of wires adjacent, above, and below affect circuit performance.

Today's LPE tools lack the insight into the vertical plane, and they depend upon equations that approximate the effects of the vertical plane. These approximations depend upon what information the LPE tool is capable of extracting and retaining, as well as on what math functions the LPE tool can support.

Factors determining deep submicron foundry capability

Today, silicon foundries producing memory and logic ICs have reached the 0.35-µm design rule and are expected to reach 0.25 µm by 1998, according to the Semiconductor Industry Assoc. (San Jose, CA). These foundries can easily produce chips containing over a million gates. Susan Billat, senior vice president of marketing at Ultratech Stepper Inc. (San Jose, CA), explains that semiconductor wafer manufacturing process consists of three major steps: (1) thin film deposition, (2) photolithographic imaging, and (3) etching. During thin film deposition, films are grown (or deposited) on the wafer surface. The photolithographic imaging process imprints the patterns that make up the circuits of a semiconductor device atop this thin film. This is accomplished by exposing a light-sensitive coating on the substrate surface with the pattern imprinted on a mask or template, known as a reticle. Etching removes selected portions of the film after the reticle pattern has been imprinted on the wafer. Photolithography steppers expose this mask pattern numerous times as they move (step) the wafer to create multiple integrated circuits on each wafer. This is known as the step-and-repeat process--hence the name, stepper. Repeated numerous times during device manufacturing, this processing sequence is critical to new IC development. In fact, the ability to develop more complex ICs with smaller features, such as 64- and 256-Mbit DRAMs, is largely dependent upon the capabilities of the photolithography equipment. The resolution of the stepper determines the minimum feature size for transistors as well as how close together these transistors and other circuit elements can be placed. Historically, manufacturers achieved smaller line widths by increasing a stepper's numerical aperture (NA). However, as NA increases, depth of focus decreases, and wafer processing becomes more complex, thus driving up costs. Stepper manufacturers such as Ultratech Stepper Inc., ASM Lithography, and others are maintaining NA, but they are using shorter wavelengths of light to achieve finer line resolution. With this technology, equipment manufacturers can allow foundries to achieve 0.25-µm process rules. Diane Hymes, manager of technical marketing at OnTrack Systems Inc. (San Jose, CA), says chemical mechanical planarization (CMP) is another wafer fabrication technology determining next-generation fab capacity. Deep submicron processes are moving toward four to six layers of metal. A close-up view of each metal layer reveals an undulating, uneven surface that must be leveled before the next layer is manufactured. Otherwise, the width of metal lines will vary greatly. CMP polishes each surface using mechanical and chemical abrasives to achieve a high level of smoothness. Cleaning systems provided by OnTrack and others removes the leftover polishing grit. One other factor governing the manufacture of deep submicron chips is the change of vias between metal layers. To achieve 0.5 µm-process rules, manufacturers had to replace aluminum vias with tungsten--a metal that offers more resistance but fills more evenly the very narrow cylindrical vias between layers. Keven Lorenzen, director of marketing at Materials Research Corp. (Orangeburg, NY), says the trend is to return to aluminum in combination with titanium and nitride. Another alternative being explored is copper interconnect; however, it is more problematic because the metal does not lend itself to conventional deposition techniques, as do aluminum and tungsten. As shown in the figure, the next-generation 0.35-µm process technology uses four layers of aluminum interconnect with tungsten vias connecting between different metal layers. It also uses advanced processing techniques, such as chemical mechanical polishing (CMP), and a new plasma etching method. Shown on the SEM photos prepared with a focused ion beam (FIB) technique, four metal lines with high-integrity are connected by well-defined tungsten vias. This interconnect technology offers a manufacturable and reliable IC process for fabricating high-density 0.35-µm integrated circuits.

A typical tool combines LVS data from a design with process-related parameters such as metal thickness, thickness of oxide between metal (insulation), contact and via resistance, etc. The designer provides this data based on information from a silicon foundry.

The LPE tool computes field solver equations to extract interconnect resistance and capacitance values. To comprehend the effects of capacitance between metal layers, the tool employs a quasi-3-D method to save compute time. The technique models capacitance from two orthogonal sides of a vertical plane, side and front.

As foundry process rules continue to shrink to 0.25 µm and below, a new generation of design tools will be needed. Already, Sematech has awarded Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Inc. (Mountain View, CA) a contract to produce the Chip Hierarchical Design System for Timing Driven Electrical and Physical Design.

Sematech is also evaluating bids for chip parasitic extraction & Signal Integrity Verification (CPE & SIV) tools. The ability to create circuits to use these next-generation process technologies will be determined by the capability of these tools.

Jonah Mcleod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  September 1996