Deep Submicron Special Section

CHDS: Next Paradigm for Deep Submicron EDA?

Even more acronyms abound, as Steve tells us how the SEMATECH member companies are addressing the "design gap."

by Jonah McLeod

Paradigm shifts are becoming common occurrences in the EDA industry. The advent of SPICE, schematic capture, synthesis, HDL-driven design, and, yes--even frameworks--were all watershed events.

What represents the next paradigm in EDA? We have heard the industry pundits talking about deep submicron design challenges. But aren't they merely incremental add-ons to today's flows? Not according to the SEMATECH member companies that are funding a large-scale effort to address the "design gap" so that design productivity can begin to catch up.

Traditional flows becoming obsolete The basic, time-tested EDA flow model used throughout the 1980s was simple: capture, then simulate, then finally throw the design "over the wall" for physical layout and feed to manufacturing. Although IC design has traditionally focused more attention at the transistor and physical levels, IC designers adopted this basic flow (with augmentation). As IC fabrication capabilities extended down to minimum feature sizes of 0.5 µm or less, the significance of interconnect delays could no longer be ignored. As a result, several enhancements began to appear in new EDA tools: non-linear delay modeling, input slope modeling, backannotation of calculated delays, and custom wire load models for more realistic synthesis constraints. These "add-ons" are used extensively today for IC designs targeting 0.35-µm design rules. In exceptionally high-performance ICs, more tricks are also being employed in clock trees using variable buffer and line width resizing, physical floorplanning, and full-chip extraction of parasitic RC effects from routing.

Unfortunately, none of those enhancements change the fundamental problem. It remains that tradeoffs in functional and physical design must be treated in an integrated fashion. Without this change, the intricate and increasingly complicated dependencies between the two cannot be effectively managed. Even at 0.35 µm, many designers face a "ping-pong" effect where a fix in one domain creates new problems in the other. Many semiconductor companies are very concerned that the EDA industry is not keeping pace with the growing design gap. While on-chip transistor counts are expected to rise from roughly 8 million today up to 100 million within the next three years, designer productivity is only rising at 10 percent per year. Huge business opportunities will be lost unless more revolutionary design flow changes are made soon.

Some of the more critical concerns include the inconsistent and often inaccurate timing equations and algorithms being employed across the design flow; too much dependence on batch file formats for data exchange; and the fact that more EDA standards are required to support user-integratable tools for optimized flows.

New tool requirements in the deep submicron era To correct the deficiencies listed above, several fundamental requirements are clear. First, the entire flow must be "timing-driven." This means that timing information for the design is available at any point in the design flow across multiple tools and abstraction levels. The key to this is a common delay engine, combined with a common way of thinking about the elemental component pieces of delay at any design stage. Also, since interconnect delay is now dominant in determining timing performance, more accurate RC-parasitic extraction based on physical routing information is critical, both for backannotation as well as in forward-driven estimation.

Second, the sheer volume of detailed data to be passed between tools necessitates that application procedural interfaces (APIs) be utilized to the greatest possible extent, especially for concurrent or iterative portions of the tool flow. Although file formats provide a persistent means of storing data, they can become very inefficient when incremental data must be rapidly exchanged between tools. APIs allow multiple "expert" tools (with their own expert library data) to make concurrent engineering decisions, exploring dozens of tradeoffs in the time it takes the user to explore just one.

The third concern is that as design complexity and heterogeneity increases, it becomes even more crucial to permit a wide array of algorithms and tools from numerous suppliers to work together. Yet accuracy and performance cannot be sacrificed when designing 20 million transistors to sub-quarter µm design rules. Thus, an integrated suite of industry standards (API-based) must be defined and adopted that all EDA suppliers will use. The concept of industry standard APIs is a key aspect of the EDA Industry Standards Roadmap document, published last year by the EDA Industry Council.

Figure 1: The Chip Hierarchical Design System tool flow integrates electrical and physical design with parasitic extraction and signal integrity analysis, using standard procedural interfaces to exchange performance data via common database and timing engines.

The final concern is that all of these capabilities must be able to support the massive amounts of design information generated. Two approaches must be implemented in tandem to pull off this feat. The entire flow must be intrinsically hierarchical and incremental. Hierarchy is needed to "divide and conquer" massive verification tasks, while cycle times require an incremental change philosophy.

The Chip Hierarchical Design System The Chip Hierarchical Design System (CHDS) was jointly specified with inputs from members of the SEMATECH Design FTAB (see "The SEMATECH design FTAB"). The CHDS statement of work consists of three subsystems, which include electrical design, physical design, and parasitic extraction/signal integrity. The first two subsystems were awarded in a single contract to Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Inc. (Mountain View, CA), with subcontractors IBM Corp. (Armonk, NY) and Cooper & Chyan Technology Inc. (CCT) of Cupertino, CA. IBM is contributing its Integrated Data Model (IDM) technology and also technology in floorplanning and physical placement, while CCT is contributing its expertise in physical routing. In additon, CAD Framework Initiative (CFI) of Austin, TX, is supplying the Delay Calculation System (DCS) technology specified in the CHDS contract. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys has overall responsibility for the system tool flow and integration.

The third subsystem addresses the needs of deep submicron chip parasitic extraction (CPE) and signal integrity verification (SIV). The CPE/SIV contract was recently awarded to Lucent Technologies (Allentown, PA), with subcontractors Ultima Interconnect Technologies Inc. (Santa Clara, CA) and OEA International Inc. (Santa Clara, CA). The objectives of the CPE/SIV contract are to provide full-chip RC-parasitic extraction with selectable prioritization between high accuracy and fast performance. Lucent is contracted to deliver a seamless CPE capability into the CHDS flow. The CHDS electrical/physical design beta software is set to be deliverable to SEMATECH member companies by November of 1997, and the CPE beta software is slated for delivery by May of 1998.

It is a primary goal that the CHDS flow becomes the "new paradigm" to enable high-performance IC design in the realm of 0.25 µm to 0.18 µm. This flow is not meant to be used solely by SEMATECH members. How does SEMATECH plan to make this happen? The key to large-scale productivity increases lies in official standardization of a common information model. SEMATECH is counting on IEEE approval and widespread adoption of both IDM and DCS, which together are referred to as "CHDStd" (CHDS technical data).

The SEMATECH participants are focusing squarely on leading-edge IC design methodologies in support of 0.18-µm design, in accordance with the SIA's National Technology Roadmap for Semiconductors (NTRS). Billions of dollars are at risk in an effort to keep the fabs full. Yet today's leading-edge IC design tool flows will become tomorrow's ASIC design flows and next week's FPGA flows. Further, systems electronics integrators are also turning to more advanced multichip packaging and interconnect technologies, where the same timing and power performance requirements apply.

Technical requirements The CHDS flow integrates electrical, physical, and CPE/SIV sub-flows with the CHDStd common delay architecture and common EDA information base (see Figure 1). SEMATECH expects this HDL-based approach to support digital designs in the range of 28 to 80 million transistors, at 0.25- to 0.18-µm feature sizes, with 6 to 8 levels of metal, and clock frequencies of 500 MHz up to 1 GHz.

As designs become increasingly complex, more designers must work in tandem to meet time-to-market constraints. The CHDS requirements specify support for geographically distributed, networked design teams, and permit multiple design methodologies. While top-down, requirements-driven design methodologies are needed for completely original designs, bottoms-up "building block" methodologies are also needed, most notably to support design reuse. "Middle-out" design methodologies are often required when combining fresh requirements with existing intellectual property.

The CHDS flow begins at the architectural and behavioral design stages. Even at this early point, interfaces with the common, persistent information-base permit best-case estimates for timing delay (based on interconnect topology and parasitic knowledge) and power consumption. Early design planning is key to managing timing variability. The CHDS design planner is expected to offer:

• Analyses for placeability, routability, congestion, capacity, and porosity.
• Interactive electrical rule checking (ERC).
• Power and clock tree planning.
• Dataflow planning and optimization.
• Hierarchical area planning.

As the design progresses to the structural/RTL level, issues, such as design for test and logic synthesis based on early functional floorplanning, begin to surface. Following electrical design, efficient detailed physical floorplanning, partitioning, placement, routing, and design rule verification occur. The next stage involves chip-level 3-D parasitic extraction, calculation of actual timing delays, and signal integrity analysis. Signal integrity issues such as crosstalk, voltage drop, di/dt noise, current density, electromigration, and substrate noise coupling are performed here. Calculated timing from parasitic extraction is then hierarchically backannotated into the delay engine. The cycle is completed by providing for hierarchical comparison of actual timing versus budgeted timing values. Timing uncertainty and error may be reported at any stage in the design flow.

Following physical placement and routing in Figure 1, chip-level parasitic extraction is performed on the physical design. The approach specified in CHDS is to utilize variable error bounding between critical and non-critical nets. Power network analysis for electromigration and voltage drop will be supported. Further, a study on inductive effects modeling is being funded by SEMATECH to determine if and how such modeling should be incorporated in the future.

Timing accuracy is the cornerstone of the CHDS architecture. In addition to the many specific types of timing constraints and timing delays, timing information is organized into a set of classes, where each class is useful for comparison against other classes. The CHDS requirements specify the following timing classes:

• Required--identified from the design specification.
• Budgeted--the designer's target timing goals.
• Simulated--obtained from simulation.
• Analyzed--results from timing or other performance analysis.
• Actual--calculated from post-physical design geometries.
• Measured--measurements from manufactured parts.
• Current--represents the present design timing.
• Other--optional timing class for user-defined design contexts.

The CHDS requirements likewise call for statistical ("variational") timing support as an integral part of the architecture. Statistical timing data can aid the designer in managing timing uncertainty across the flow, such as balancing design tradeoffs against the risk of timing violations, or identifying portions of the design where timing discrepancies are less likely to converge. Statistical timing types include: distribution, nominal, mean, minimum, maximum, sigma, confidence level, skewness, and kurtosis.

To support microprocessor-style IC designs, the CHDS requirements call for pre-layout parasitic estimation capability. This estimation will be based on preexisting design and cell libraries from prior design implementations, and/or partial physical design results. The goal is to extract useful empirical knowledge about parasitics from existing physical data and apply it to improve estimation accuracy.

Path-fixing support will also be included to analyze timing errors and propose one or more design process steps to correct the timing violation. This support includes:

• Parasitic sensitivity analysis for prioritization of marginal timing paths.
• Resizing of transistors and addition/subtraction of repeater transistors.
• Adding marginal paths to a list of paths subject to incremental rerouting.
• Ability to invoke dynamic timing checks on specified paths.

Numerous additional advanced capabilities, spanning inductive effects, dynamic logic, thermal and process variations, are also specified as part of the CHDS requirements.

Issues surrounding CHDS The full CHDS flow is a massive undertaking, covering a wide array of detailed requirements too numerous to list here. Yet, there are several critical constraints and limitations to consider.

Digital hardware scope The CHDS flow is specifically focused on requirements for digital design. Although a number of SEMATECH members anticipate some amount of analog or RF functionality interspersed with digital logic, a conscious choice was made to keep a digital focus for the following reasons:

• VLSI IC designs will continue to be dominated by digital functionality.
• Digital interconnect delay timing is the key issue driving a paradigm shift in EDA flows.
• High-performance digital IC design is already a massive effort. Additional scope would add much greater risk.
• Funding levels and qualified contractors were a limiting factor.

Another aspect of digital ICs is embedded software, which was taken to be out-of-scope. More fundamental changes must occur at the functional description level to accommodate true hardware-software codesign. However, CHDS requirements dictate that C/C++ will be reviewed for potentially useful timing information.

There are other high-level issues identified with "systems on silicon" design flows not being addressed here, such as requirements capture, formal verification alternatives, and design reuse. However, CHDS requirements include the ability to accept pre-designed hard macros and soft (RTL) macros.

Performance metrics While SEMATECH members expect overall productivity improvements in the range of 4x, few performance metrics were given for assessing compliance in a CHDS tool suite. A vast number of capabilities are very clearly stated as requirements, most with substantial functional detail. Even so, those capabilities would mean little if not completed within reasonable execution times.

Database implementation The central information base that processes all API requests for design data is actually an object-oriented database whose schema is defined by CHDStd. Even with CHDStd destined for official IEEE standardization, the real objective is for multiple suppliers to offer CHDStd-compliant database implementations. One contract partner, IBM, has agreed to deliver its internal implementation as part of the beta-site software, but has not committed to produce it for external sale. Some believe that industry-wide success will require timely support from multiple suppliers and that production-quality products must be available shortly after the end of the contract period.

A level playing field? Whenever a contract is awarded to one of many competitors in a given market, it is not uncommon to hear concerns that those not a part of the contract are at a comparative disadvantage, and may be disinclined to embrace the industry goals of the contract. In this case, however, very little concern has been aired regarding free competition. Instead, several observers have noted only that CHDS could be undertaking too much at once to accomplish lasting industry-wide change.

The SEMATECH design FTAB

SEMATECH is a consortium of U.S.-based semiconductor companies, formed in 1984 with the mission to "create shared competitive advantage by working together to achieve and strengthen manufacturing technology leadership". Member organizations include: AMD, Digital, DARPA, Hewlett-Packard, IBM, Lucent Technologies, Motorola, National Semiconductor, Rockwell, and Texas Instruments. Even though SEMATECH's mission is clearly focused on manufacturing, members realized that the growing "design gap" posed a threat to future growth as predicted by the SIA National Technology Roadmap for Semiconductors. As a result, four new functional technical advisory boards (FTABs) were formed in 1993 to address issues in Design, TCAD, Test, and Assembly & Packaging. Greg Ledenbach, director of The Design, TCAD & Test Division, notes that "the CHDS design flow is actually targeting paradigms to support 0.18-µm design processes, and may possibly be useful as far down as 0.10 µm . CHDS is labeled as a 0.25-µm design system because that is the generation for which the first commercial use of the tools are supported. The 0.25-µm system availability allows our suppliers to begin to reap the financial benefits of the SEMATECH joint development contracts." Ledenbach emphasizes that the Design, TCAD and Test Division is funding a TCAD study of inductive effects to prepare for new 0.18-µm challenges, and he states the need for new EDA standards. "EDA standards and a common information model are the keys to future productivity increases," he said.

Industry perspectives So far, we've discussed the objectives and requirements of the CHDS contract. But what about support from the rest of the EDA industry? According to Glenn House, vice president and general manager of Mentor Graphics Corp.'s Silicon Systems Division (Wilsonville, OR), the need for support is clear. "The question will be: 'How well does this approach address the need?'," said House. "Historically, these projects do not directly lead to successful products, but they provide a necessary exploratory learning that results in a second generation of products. Mentor supports the project, and if the API approach provides sufficient bandwidth, we will adopt it. Mentor sees a competitive edge with the capacity and performance of our Forma database, and having IEEE standards are good for us because they lower the cost of tool development."

Jim Douglas, vice-president of product marketing at Cadence Design Systems Inc. (San Jose, CA), says the "CHDS vision is right on," but the challenge will be successful implementation. "I'm skeptical, because past attempts to hit home runs by committee usually don't work. Will it be transferable knowledge? Will it scale to improve the entire industry? It's very difficult to do this much at once; more tangible pieces tend to be successful. But it creates a methodology pull, and we have an opportunity to run with some of the standards in CHDS for an improved flow".

George Janak, CEO and founder of High Level Design Systems Inc. (Santa Clara, CA), states that market opportunity will drive their support of CHDStd. "With reasonable early market acceptance of the contract deliverables, we would adopt CHDS," said Janak. "We have the database repository and APIs (through Pillar), and we have been quietly bolting on pieces to support semiconductor customers. If our EDA partners add API interfaces, we have the infrastructure. But the contract amounts aren't sufficient to fund all the engineering technology needed for CHDS--can they deliver?"

What advice do each of these industry representatives have to offer readers? "It takes three elements: world-class linchpin technology, libraries of RTL through physical design macros, and design methodologies--not just services--to tie them together", said House. Douglas asks readers to "watch CHDS to see if it bears fruit, and have an awareness that a serious methodology shift is coming, although many don't realize this yet". Janak states that "if you spend too much time in synthesis, you need to make the shift, starting at RTL level with parasitic estimation. Designers must understand how to accurately model for timing."

Future directions for CHDS With millions of dollars at stake in the CHDS contracts, SEMATECH Design FTAB members have high expectations for the future design capabilities to be delivered at the close of the contract. However, because of the inherent diversity of tools needed for leading-edge IC design, the real key to success is widespread adoption across the entire EDA industry.

The IEEE Design Automation Standards Committee (DASC) has recently established a new working group for the CHDStd information model. Assuming a successful CFI ballot in Q2 of 1997, CHDStd could be an IEEE standard as early as Q4 of 1997. This would have a substantial effect on increased confidence for enabling consistent adoption.

But what does all this mean if you are not designing 0.25-µm ICs? It is perhaps too early to tell, but historical trends show that advancements made in state-of-the-art EDA flows provide real benefit to all users of EDA tools over time. ASIC toolkit suppliers are already beginning to see the need for more substantive changes ahead in both tool flows and design methodologies. FPGA suppliers will eventually have a similar need for improved timing and power predictability as FPGA densities and performance continue to increase. Unfortunately, the coarse-grained architecture of FPGAs will mean additional work to take full advantage of the CHDS-style flows. For systems electronics designers, the benefit may be more direct than expected. In addition to the overall increased systems performance enabled by integration of advanced ICs, systems timing issues also have substantial interconnect delay and signal integrity issues. MCMs, PCB backplanes, and cabling concerns all share the need for new EDA paradigms.

If successfully adopted, a standard API-centric information model will also permit more niche players to "plug and play" within the pivotal core of high-accuracy EDA flows, enabling greater choices of algorithms and tools.

This vision will require the support of today's EDA customers, who must add their influence to ensure adoption by all major EDA partners. In particular, it is critical that the current CHDS contract primes ( Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys and Lucent) emphasize the new API paradigm, and tune its performance to support next-generation designs. Designers should expect nothing less.

Contributing editor Steven E. Schulz, P.E., is a senior member of the technical staff at Texas Instruments (Dallas, TX).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  December 1996