Special Section

Design SuperCon '96: Coping With Increasing IC Complexity Designers share their experiences building complex ICs and FPGAs. by Jonah McLeod

ASICs are now getting so complex that entire systems can be contained on a single piece of silicon. At the same time, FPGAs are extending well into the low-end range of ASICs. The challenge for designers is developing new design methods that help master this complexity to meet short time-to-market windows.

During the 1996 Design Supercon, running from January 30 to February 1 at the Santa Clara Convention Center, the technical presentations in the "On-Chip System Design Conference" will provide a variety of solutions for designers. One set of papers will address the complexity created by the increased amount of software incorporated into high gate-count ICs. A second set will deal with design verification of hierachical netlists­ensuring all the changes in a netlist do not change the original specification of a million gate chip. And the third set will explore how growing FPGA density is demanding ASIC methodologies for these reconfigurable chips.

To effectively deal with complex system designs requires a new breed of tool and methods that have been lumped under the heading, "electronic system design automation" (ESDA). Frank S. Eory, senior electronic design engineer in the Satellite Communications Division of Motorola, Inc. (Chandler, AZ) relates his experience in using new high-level design tools. In his paper, "DSP ASIC Design and System Simulation for Wireless Communications," Eory says "the objectives of our project team were to design and verify through simulation a high-performance satellite modem.

Eory's team included communications system, software, mechanical, and test engineers, as well as RF circuit and digital ASIC designers. The team used the Signal Processing WorkSystem from Alta Group, subsidiary of Cadence Design Systems, Inc. (Sunnyvale, CA). The Alta Group's Signal Processing WorkSystem enabled Eory's team to model the modulator, the communications channel with noise added, and characteristics of the modem receiver front end (See Figure 1 ).

Figure 1. Tools such as the Signal Processing WorkSystem from the Alta Group, subsidiary of Cadence Design Systems, Inc. (Sunnyvale, CA) allows designers to simulate entire communications systems.

Observing the behavior of a design at this high level, design teams can make design trade-offs not possible at lower levels of abstraction. For example, designers might trade-off a general purpose DSP for a dedicated DSP or one brand of DSP with another. Designers can also examine the impact of increasing or decreasing the amount of memory in a circuit. Can the design contain enough functionality to fit into a PCMCIA for factor?

James P. Davis, vice-president and chief scientist at Knowledge Based Silicon, Corp. (Columbia, SC) presents high-level design techniques that are at a level of abstaction below the one Eory and his team used. In his paper, "High-Level Design of On-Chip Systems for Integrated Control and Datapath Applications," Davis introduces two tools­ blockHDL and flowHDL. With these tools, designers can describe the finite state machines and datapaths of a design at the behavioral level. Furthermore, the tools create HDL code ready for synthesis.

In his paper, "Statecharts­Better Than Better State Machines," Moshe S. Cohen, director of Statemate product family at i-Logix, Inc. (Andover, MA), argues against state machines. Statecharts, he asserts, offer a behavioral and graphical hierachy; state machines only offer a graphical hierarchy.

One result of the increasing development of embedded processor systems on a silicon chip is the explosion in the amount of software contained in these designs. In his Design Supercon paper, "Hardware Software Co-Simulation," Jauher Zaidi, ASIC development manager at Quantum, Corp. (Milpitas, CA), states that a disk controller chip he developed took six months of ASIC design and five and a-half months of software simulation. To cope with these long hardware and software development cycles, designers are performing the tasks concurrently.

For concurrent hardware-software development to occur, there must be some method to ensure that software runs on the final ASIC being developed. In the past, the two efforts occurred autonomously, followed by a tedious integration step that typically lasted weeks. However, the time needed to integrate the two efforts after both are complete is no longer available. As a result, design teams are reverting to hardware emulation to solve the problem.

Return of the hardware prototype Brian Levy, CAE productivity engineer at Hewlett-Packard Vancouver Printer Division (Vancouver, BC), explains one solution. In his paper, "Early Firmware/Hardware Integration and Verification Using Hardware Emulation," Levy describes how his design team built a hardware prototype of an ASIC controller for a new HP ink jet printer.

Levy's group used an HP64700 in-circuit emulator for the embedded processor in the ASIC. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys Logic Group's (Beaverton, OR) Hardware Modeller and Smart Models provided ROM and RAM for the emulator. Finally, the ASIC logic under development was loaded into FPGAs from Xilinx, Inc. (San Jose, CA). All of these components were integrated onto the Explorer Hardware Emulator from Aptix, Inc. (San Jose, CA). The emulator contains a high-speed switching matrix that allows various components to achieve very high switching speeds.

Levy states the prototype ran at 4 MHz, one-fourth of the 16MHz speed of the final ASIC. But the big payoff came in time-to-market; the firmware was running four months ahead of first silicon and final system integration ran a full month ahead of original schedule.

However, Jeff Freeman, principle staff engineer in the High Performance Embedded Systems group of Motorola, Inc. (Austin, TX), achieved similar results using a rapid prototyping methodology containing soft-ware models. In his paper, "ColdFire Rapid-Prototyping Design Methodology," he describes a complete simulation environment. It contains a system model of the embedded microprocessor, as well as external bus, memory, and development system models to stimulate the on-chip debug module. Freeman's team executed actual program code from memory. The software development team was able to enter debug commands such as breakpoint, read/write registers, etc.

The real benefits of rapid prototyping are rapid design complexity expansion and shorter time-to-market windows. Sanjay Sawant, product marketing engineer at Quickturn Design Systems, Inc. (Mountain View, CA), in his paper, "Using RTL Emulation to Exhaustively Validate HDL Design Description," states that by 1996, 45% of all designs will be over 100,000 gates. In addition, the average product life of these designs have declined by a factor of four.

To put the various solutions into perspective, Sawant notes that simulators running 300,000 events per second can simulate a millisecond of system operation every 42 minutes. A full second takes 28 days. Hardware accelerators can simulate a millisecond of operation in 100 seconds, but a full second of operation still takes 28 hours. Hardware emulators perform a millisecond of real-time operation in 12.5 millliseconds and a full second in 12.5 seconds.

Figure 2. Design VERIFYer from Chrysalis Symbolic Design, Inc. (N. Billerica, MA) allowed Cray Research (Chippewa Falls, WI) to verify 50,000 gate netlist in only four hours.

Verifying complex hierarchical designs To comprehend the complexity of these hardware systems, designers are expressing their designs as a hierarchy containing behavioral blocks, RTL descriptions, logic gates, and transistor circuits. As a result, the major problem designers confront is verifying that changes in any one of these hierarchical descriptions is consistent with the original system specification.

Simulation-based verification requires comparing a design against the original specification," says Geoff Barrett, verification engineer Chameleon project at SGS Thomson Microelectronics, Ltd. (Bristol, England). To do so demands a complete "golden" test vector set, simulating the design with the vectors, and verifying that the resulting output vectors are correct." Barrett and his team built a 5million transistor multimedia processor. In such large systems, this method is too time consuming to be practical.

Designing a high-speed graphics subsystem on an ASIC

With the advent of high-resolution images and video onto PCs and workstations, the graphics subsystem of these computers have become glaring bottlenecks. These logjams result in choppy video displays, small image size, and picture quality poorer than television. To solve this problem, graphics system designers are embracing completely new architectures. At the 1996 Design SuperCon, Integrated System Design magazine is sponsoring one paper on this major design issue. Billy Garrett, manager of graphics development at Rambus, Inc. (Mountain View, CA) and Tom Chai, senior manager of research and development at NEC Electronics, Inc. (Mountain View, CA) will give the presentation entitled, "Designing a Graphics Controller with a 1GB/s Memory Interface." In the paper, Garret describes the process of creating a graphics controller chip. Garrett and his team captured the design in Verilog, simulated it with Verilog XL from Cadence, and synthesized a gate-level description with HDL Compiler from Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys . An NEC mixed-analog and digital floorplanning tool and Cadence's Cell3 place and route tool created the final layout. At the core of the presentation is the Rambus Universal Graphics Back End (RUGBE) technology, jointly developed with NEC. Implemented in a 0.5µm IC design process, the technology achieves display resolutions of up to 1600 by 1200 with 24 bits-per-pixel true color support. Furthermore, the device provides this display capability at a frame buffer bandwidth of 1Gbyte per second. The screen-shot below shows the chip's capability. A complete graphics subsystem comprises two Rambus DRAMs and the RUGBE controller. A typical Windows display that the chip creates is shown in the accompanying figure. Contained in 25,000 gates, the controller includes only a hardware cursor and no other acceleration features. However, a designer can implement the circuit in a larger ASIC and add hardware acceleration features to suit his application: engines for bitblt, line drawing, pixel drawing, etc. The presentation runs from 1:00 PM to 2:00 PM in the multimedia theater of the Santa Clara Convention Center on January 31, 1995.

In a paper Barrett co-authored with Dino Caporossi, product manager of Compass Design Automation, Inc. (San Jose, CA), entitled "The Use of Formal Verification in a Mixed Methodology 5 Million Transistor Multimedia, Microprocessor," the two described how the VFormal verification tool from Compass was used. Barrett's team also wrote two programs, Winnow and Shadauc, and also used SMV, a university program, to perform sequential verification. (For more information see the feature article in the January 1996 issue of Integrated System Design. )

One major benefit of formal verification is the ability to verify a design more accurately and much faster than with simulation-based verfication. Another plus is the ability to verify a gate-level description against a VHDL specification of the circuit.

In his paper, "Formal Verification of Complex ASICs in a Production Environment," Doug McTavish, manager of design verification for the MPP Division of Cray Research (Chippewa Falls, WI), describes Cray's experience with formal verification. McTavish's team created three one-million gate ASICs and one 500,000 gate ASIC. The ASICs combined with a 21164 Alpha processor from Digital Equipment, Corp. (Maynard, MA) to form one T3E Processor Element in the Cray massively parallel supercomputer.

McTavish's team used the Design VERIFYer from Chrysalis Symbolic Design, Inc. of N. Billerica, MA (See Figure 2 ). It is similar to the Compass tool in that both handle about 50,000 gates at a time. McTavish says that verifying a 50,000-gate segment of his design against the "golden" RTL description, took 30 minutes of compile time for the gate and another 10 minutes for the RTL. Thereafter, the verification itself took another 200 minutes. He estimates that overall formal verification took about one-third of the time of a simulation-based alternative. The design flow which the McTavish's team used is shown in Figure 3 .

Figure 3. The elements contained in a large ASIC designer Gloria Sun and her team at 3Com, Corp. (Southboro, MA) built helped implement the functions of a 100 Mbit Ethernet product.

Formal verification is unique from simulation-driven verification in that the logic of the circuit being verified is not functionally tested. Rather, the circuit is compared against the original specification. The comparison determines if the new circuit is functionally equivalent to the original.

Simulation-based verification One drawback to formal verification is that it necessitates a change in methodology for most designers. Thus, simulation-based verification continues to be the preferred solution­even for complex chip designs. In her paper, "Design Verification of a Complex 100 Mbit Ethernet Switch ASIC," designer Gloria Sun, of 3Com, Corp. (Southboro, MA), describes the design of a 100-Mbit Ethernet switching ASIC, using QuickSim II from Mentor Graphics Corp. (Wilsonville, OR).

One element of a larger mezzanine board, the chip is a full- duplex, non-blocking design that handles bursty data from the 100 Mbit Ethernet and the multi-link switching engine. Sun explains that to speedup the verification, her team used hardware models of functions surrounding the ASIC being developed (see Figure 3 ). The task was eased by having the IEEE 802.3 standard MII interface as the simulation boundary. A random packet generator provided varying packet length, patterns, gaps, etc. to create a more realistic traffic pattern. Sun's group was able to process 400 packets per simulation run. Each run lasted around 30 hours.

Motorola Inc. and IBM Corp. (Austin, TX) also implemented simulation-based verification on the PowerPC microprocessor family. Guna Thuraisingham, logic design engineer for PowerPC at the Somerset Design Center (Austin, TX) describes a two-simulator environment for design verification. Using Texsim, the design center's own two-state behavioral simulator, and Verilog XL, from Cadence (San Jose, CA), the Thuraisingham group achieved a billion random bug-free cycles during a full-chip simulation.

Field programmable gate arrays Just as design complexity is forcing changes in design methodology in million-gate ASICs, so too are 50,000 gate FPGAs compelling changes in engineering processes for these devices. Stephen L. Wasson, engineering consultant at HighGate Design, Inc. (Saratoga, CA), discusses one such change. In his paper, "Level-Compression Techniques for High-Performance FPGA Design," he explains the concept of level compression.

In a large part of the presentation, Wasson describes the logic-level analysis used to generate the DEVSEL signal in the Peripheral Component Interface (PCI) bus target function. Implementing level compression, Wasson asserts that the designer is putting the FPGA constraints ahead of design constraints by designing to the target architecture.

"The immediate goal of level compression is logic-level reduction; how and what to reduce depends upon performance trade-offs made throughout the design process," he says. "By understanding and designing to a target device's granularity, the designer may make intelligent trade-offs between device selection, macro instantiation, design implementation, and logic reduction."

One advantage level compression affords is reducing routing delays; this equates to maximizing performance margins. Level compression also optimizes logic mapping which reduces the routing resouces used and, thus, provides better device utilization. The technique also reduces the size of the FPGA for a given design and cuts time-to-market by reducing the number of design iterations needed to fit a design into a device.

One major new direction in FPGA design is from schematic-based entry to Verilog and VHDL language entry, says Sid Gilbrech, senior hardware design engineer at 3COM Corp. (Santa Clara, CA). In his paper, "FPGA Flexibility Enables Concurrent Board Design and Layout," he states, "these languages allow complex designs to be described much more efficiently than schematics."

Gilbrech says schematic-entry will still be used for performance-sensitive applications. The design flow he envisions is shown in Figure 4 . "Being able to quickly make changes, compile those changes, and see the results in simulation are the keys to fast design development," he asserts. Other benefits to language-based design include freeing the designer from the place and route chore.

In his paper, "RAM Based FIFOs in FPGAs Enable Board Real Estate Consolidation," Mark J. Lever, of Applied Digital Access, Inc. (San Diego, CA), presents an FPGA designed from the top down using VHDL. Lever chose the Model Technology Inc. (Beaverton, OR) VHDL simulator to verify the design. He automatically synthesized the resulting description using Design Compiler from Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys , Inc. (Mountain View, CA).

Lever's team built an add-in board for switching between a high-speed DS3 telephone link and a Sonet STS-1 link. The team implemented much of the design in new Xilinx 4000E and 5200 family FPGAs from Xilinx, Inc. (San Jose, CA) to achieve faster time-to-market. Lever praises the FPGAs for allowing fast design iterations and providing a prototype platform for software development. However, he complains about the lack of capacity in the FPGAs and limited reuse of VHDL code.

Raymond J. Andraka, chairman of Andraka Consulting Group (North Kingstown, RI), discusses high-level design verification and explores bit serial processing in his paper, "Building a High-Performance Bit Serial Processor in an FPGA." In creating the design, he employed the CORDIC magnitude algorithm. The algorithm implements a vector magnitude processor inside a radar signal processor. The bit serial processor in the radar processes 8 million, 12-bit vectors per second. It is implemented in a single FPGA from National Semiconductor, Corp. (Santa Clara, CA). For design verification, Andraka used the Viewsim Simulator from Viewlogic Systems, Inc. (Marlboro, MA).

Figure 4. Sid Gilbrech, senior hardware design engineer at 3Com, Corp. (Santa Clara, CA), sees a software development environment for FPGA design that will allow a combination of schematic and HDL circuit capture.

One trend occurring in FPGAs is the advent of reconfigurable logic. Steve Casselman, founder and president of Virtual Comptuer, Corp. (Reseda, CA), describes the concept in his paper, "Hardware Object Technology, Implementing Digital Designs as Software Routines from within Applications Programs."

"Reconfigurable computing systems use the reconfigurable aspects of FPGAs to implement an algorithm," he says. "The advantage of these computers is the hardwiring of software and the potential dramatic performance gains due to this technology."

Casselman's company offers the EVC1 reconfigurable computer­a workstation add-in board. It is an S-Bus board containing a single Xilinx XC4010 or XC4013 FPGA. The logic of the FPGA can be reconfigured in 50 milliseconds; however, the trick is creating the unique software loaded into the programmable device. Casselman calls the programs hardware objects. They are algorithms implemented as dynamically downloadable hardware designs.

Hardware objects are created using schematic or either the VHDL or Verilog language. Casselman's paper describes Hardware Object Technology­the method used to program reconfigurable computers. He describes the conversion of a Fibonacci Sequence Generation algorithms into FPGA logic. With the algorithm programmed into a 20MHz EVC1 board and the board inside a 40MHz workstation, the hardware version ran eight-times faster than the software version of the algorithm.

Casselman's paper and others testify to innovations that solve the problems increasing IC gate capacities have created. The 1996 Design SuperCon conference offers many more, over 50 papers and panels in total, that address all areas of integrated circuit design.

Forums promise lively debate on major IC design issues

The technical panels are major attractions at any technical conference. The On-Chip System Design portion of the conference promises several panels and special events that are sure to interest attendees: two panels will discuss aspects of deep submicron design; a third, will evaluate VHDL and Verilog; a fourth, looks at library cores; and a fifth panel answers the question­when is a design ready for fabrication? One of the deep submicron panels is entitled "Exploiting High-Performance Deep Submicron Designs." Moderated by Jonah McLeod, the panel will discuss how current design methods have changed to accommodate the special needs of designs implemented in process technologies below 0.5µm. At these smaller geometries, interconnect delays exceed gate delays. Thus, the lumped-sum capacitance delays that IC vendors are currently supplying to designers are inadequate estimates of timing in this new process regimen. Furthermore, most of the front-end tools currently available do not interpret timing data supplied by IC vendors in a consistent manner. Thus, the metric used to determine if a design meets its timing spec is not deterministic. The panelist include designers as well as representatives from tool suppliers and IC vendors. Each will discuss the solutions they see to the problems deep submicron processes have created. The second deep submicron panel discusses floorplanning­a means of providing more accurate timing information to the front-end designer. Floorplanners allow a designer to place the major blocks of his design as well as place the elements within each block. From this placement, timing can be extracted and back-annotated to a synthesis netlist for more accurate timing verification. This session will be broadcast to the National Technical University (a nationwide, closed-circuit television network) and over the Internet. Two designers will describe their experiences in using floorplanning tools. Thereafter, a panel­moderated by Jonah McLeod and consisting of the two designers and two representatives from floorplanning tool vendors­will answer questions from the attendees and on-line participants. A third event combines Design SuperCon '96 attendee participation with a panel discussion. In the first part of the event, a number of conference attendees will participate in a contest to create a design using VHDL or Verilog. A special room containing Hewlett-Packard workstations will be set aside for participants to enter and simulate their designs. John Cooley, president of USE/DA and an independent consultant specializing in High-Level Design language capture, created the circuit being used in the contest. He is also directing the event. The participants who successfully complete the design will be judged on design originality and accuracy. The winner receives a cash award; however, everyone benefits from the shared experience. To discuss the shared experience, a panel will be held a day after the event; at which time, the winner of the contest will be awarded. In addition, panel members will discuss the merits of the various designs submitted for the contest. Unique design solutions will be evaluated and discussed. Library cores is the topic of the fourth panel. Moderated by Earl Reinkensmeyer, it is aimed at application specific integrated circuit designers, suppliers, and their customers. The panel will discuss the advent of new intellectual properties contained in these complex cores and the experience customers have had using the cores. Panel members will also discuss the problems of creating and maintaining library cores as process technologies quickly evolve from 0.5µm to 0.25µm and, eventually, to 0.18 µm. The fifth panel will examine the tough question­when is a design complete and ready for fabrication? It will be moderated by David Brier, professional services consultant at Mentor Graphics, Corp. (Dallas, TX); Dr. Stefan Thomke of Harvard University will also participate. Thomke recently published the result of his study on the topic. He will share some of his findings as well as contribute to the panel discussion. In the past, SuperCon panels have provided lively controversial discussions of current topics. This year promises to maintain the SuperCon tradition.

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  February 1996