System Design

Full Mixed-Signal Simulation Can Dramatically Improve a Design Process

Building a GSM phone chipset with first-time success requires a toolset with mixed-signal simulation capabilities.

by Lawrence Rigge and Steve Vandris

With both an analog and digital portion to contend with, mixed-signal ICs can make verification a challenging task. As a result, designers of mixed-signal ICs traditionally have partitioned the design at the beginning of the development cycle into analog and digital blocks, running separate digital and analog simulations. The chip is approached as a whole only at the end of the design cycle.

Although the process works well on relatively simple chips with small analog content and minimal interaction between the analog and digital blocks, such chips are more and more a thing of the past. Increased chip complexity, shortened life-cycles, and more mixed-signal designs with significant analog content and tight interaction between analog and digital blocks have made simulating the entire chip from the beginning of the design essential.

Unfortunately, such an accurate simulation is impossible using the old technique--a problem we confronted at AT&T Microelectronics when designing our GSM cellular system. GSM, Europe's digital-cellular standard, promises to be a market of enormous importance in the future. Its popularity pushes the demand for DSP chips, meaning we felt the mixed-signal design constraints acutely.

We used Bell Labs Design Automation's ATTSIM to address these design constraints. The result was higher probability of success on the first-pass silicon, lower development costs, and faster design intervals.

Figure 1. ATTSIM allowed full mixed-signal simulation of the three chips comprising a GSM cellular phone.

ATTSIM and the CSP1088 We used ATTSIM to simulate our Sceptre platform for the GSM cellular system. The Sceptre platform offered by AT&T Microelectronics consists of three chips, the AT&T DSP 1618 baseband and voiceband processor, the AT&T CSP1088 codec/modulator/timer, and the AT&T W2020 RF transceiver. Together with a power amplifier, power controller and host microcontroller, Sceptre forms a complete solution for GSM digital cellular terminals (see Figure 1 ).

ATTSIM was especially useful when simulating the CSP1088, which contains several analog-digital boundaries. The CSP1088 is a complex mixed-signal device that serves as the interface between the DSP1618 DSP baseband/voiceband processor and the AT&T W2020 RF transceiver in a GSM mobile telephone. It interfaces with the microphone/ speaker and handset, performing the baseband and voiceband A/D and D/A conversions, the baseband reception and transmission with buffering for transfer to the DSP, the GMSK modulation to GSM standards with frequency correction, and the generation of the timing and control functions for the GSM mobile applications and on-chip frequency synthesis. Figure 2 shows a block diagram of the CSP1088.

Major building blocks of the chip include a voiceband A/D and D/A converter--two receive A/D and three transmit D/A converters, analog filters, timing and control state machines, transmit and receive buffers, ciphering, and a phase-locked-loop (PLL) for on-chip frequency synthesis. The chip is an aggressive mixed-signal design, composed of approximately 70 percent digital and 30 percent analog functions.

When designing the CSP1088, we used a top-down design methodology with design and verification performed at the behavioral, functional, circuit, and mixed levels of abstraction (see Figure 3 ). First, the Sceptre system architecture was developed from the GSM system specification. Using hardware/software partitioning, we specified and modeled the hardware functions for the CSP at the behavioral level. Using the analog CSP portions, we modeled with s-domain equations and analyzed with MatLab and MathCAD. The software algorithms for the programmable DSP were developed using Alta's Signal Processing Workbench (SPW).

Simulating the CSP1088 We first used ATTSIM for functional-level simulation. We modeled and simulated both the digital and analog portions of the CSP1088 with C-models in ATTSIM--at the RTL-level for digital and as time-domain state equations for analog. ATTSIM then simulated the time-domain, mixed analog/digital behavior of the circuit and generated digital and analog waveforms.

The simulation accurately modeled the interaction between the analog and digital blocks and allowed verification of circuit connectivity and signal path integrity. The models, through their dramatically increased design speeds, also permitted whole-chip simulation and verification against chip design specifications as well as architectural exploration of the digital and analog sections. This occurred at the functional level before transistor-level implementation.

The behavioral/functional-level modeling of this methodology allowed hardware/software co-simulation, including analog circuits. This type of modeling is crucial for first-time silicon success of complex mixed-signal designs such as the CSP1088. During transistor-level verification of the CSP1088 analog building blocks, we performed mixed-level, behavioral and transistor simulation in ATTSIM to speed up the simulation. We typically modeled the digital portions at the behavioral level and the analog portions at the transistor level.

Design engineers unfamiliar with behavioral models may see ATTSIM's extensive use of behavioral modeling as a drawback. But learning to write behavioral models is a one-time effort, and we feel the advantages for the CSP1088 chip demonstrate the value of learning this new technique. Behavioral models offer tremendous potential reusability. They can be used with minor variations to seed new designs, allowing the designer to evaluate them before implementation. But more importantly, it is the behavioral models that account for ATTSIM's dramatic reductions in design interval times.

For example, the phase-locked loop was modeled using mixed digital and analog behavioral models and simulated for 400 microseconds of simulation time to verify proper frequency-locking and stability under all modes of operation. We then replaced the analog portions with transistor-level implementation and simulated for the same length of time in mixed-level mode with the digital blocks at the behavioral level. The results were compared against the functional simulation results, verifying that the analog transistor-level implementation matched the functional design. The same level of rigorous verification and confidence in the design would not have been possible with a conventional analog circuit simulator or with separate digital and analog simulations because of the tight feedback between the digital and analog blocks of the PLL.

Figure 2. Major components of the CSP1088 includes a voiceband A/D and A/A converter, analog filters, timing and control state machines, transmit and receive buffers, ciphering, and a phase-locked loop for on-chip frequency synthesis.

CPU times for the different PLL simulations are shown in Table 1 for ATTSIM mixed-digital/analog behavioral simulation; mixed-level, digital behavioral/analog transistor-level; and for comparison, SPICE-type, transistor-level analog circuit simulation using simplified transistor models for the digital transistors.

Behavioral analog simulation was 150 times faster than transistor-level circuit simulation. It would have taken one month of CPU time to simulate the PLL in the SPICE-type circuit simulator, versus six days for mixed-level or five hours for behavioral simulation. With speed improvements of this nature, one month becomes an unacceptable delay. It is also impractical to check all the operational modes of the design in a circuit simulator. The fast simulation time of behavioral analog simulation is extremely useful for architectural exploration of the analog portions and for quickly iterating to optimize the design.

Performing analog behavioral simulations does not mean compromising accuracy. Using the actual waveform measurements captured on the testbench from the real device, Figure 4 illustrates a comparison between the behavioral- and transistor-level simulations. The output in the transmitter channel is used for comparison. The waveforms shown are TXI_DEV, for mixed-level, behavioral and transistor ATTSIM simulation; TXI_BEH, for behavioral ATTSIM simulation; TXI_CKT, for SPICE-type circuit simulation; and TXI_MEAS, for the measured waveform.

While there are minor differences in the measured results compared to the simulation, all waveforms are consistent with each other, and the mixed behavioral/circuit-level and circuit-level waveforms nearly overlap. These results show that analog behavioral simulation can provide valuable and accurate information during the iterative design process.

Figure 3. The hardware functions for the CSP were modeled at the behavioral level. The software algorithms were developed using the Alta Group Signal Processing Workbench.

ATTSIM uses additional techniques beyond the traditional transient analysis algorithms to improve the speed of analog transistor-level simulation. Traditionally, an analog simulator evaluates the entire analog circuit without discriminating between active and inactive areas. ATTSIM, by contrast, divides an analog circuit into parts and performs separate simulations for each portion of the circuit, allowing each analog portion to be evaluated at its own rate. When a particular portion has reached steady state, evaluation ceases for that portion and does not begin again until there is new activity. The result is increased speed on the order of five to ten times, depending on the nature of the circuit and the extent to which it can be partitioned.

System environment simulation But simulating a mixed-signal device like the CSP1088 by itself is not enough. Therefore, a key aspect of the behavioral modeling design methodology is to ensure that the chip operates properly in its surrounding environment. To do so, we used ATTSIM to perform a system-level simulation of the complete system environment, including the CSP1088 device. We integrated a clock-phase accurate model of the DSP1618, called the Interactive DSP Model (IDM), into the simulation environment and emulated the handset and RF interface using ATTSIM simulator driver/monitors.

Figure 4. The waveforms shown are TXI_DEV, for mixed-signal, behavioral, and transistor simulation; TXI_BEH for behavioral simulation; TXI_CKT for SPICE simulation; and TXI_MEAS for measured waveform.

ATTSIM

ATTSIM is a single core mixed-signal simulator from Bell Labs Design Automation (Murray Hill, NJ). It simulates the analog and digital portions of a mixed-signal IC concurrently for a much higher probability of success on first-pass silicon. Most mixed-signal simulators on the market today still perform separate simulations for the analog and digital portions of a chip. But pure analog simulators understand only continuous time, and pure digital simulators only discrete time, making this technique a limited solution. ATTSIM still represents analog signals continuously and digital signals discretely. But in a major departure from the past, it uses both representations for signals at the analog-digital boundary. This key difference minimizes information loss and provides for robust mixed-signal simulation, while allowing additional flexibility for efficient mixed-signal initialization--another common problem with traditional mixed-signal solutions. In addition, ATTSIM provides multi-level modeling capability for simulation at more than one level of abstraction on both the analog and digital portions of the IC, resulting in two major benefits. First, it allows the designer to choose the most appropriate level of abstraction for each block in a circuit, allowing lower simulation complexity and faster full-chip simulation. Second, and more important, it allows the designer to verify that the implemented individual analog blocks operate properly in their surrounding environment. Furthermore, the use of extensive analog behavioral modeling allows design engineers to reuse pieces of one design in another to ease the increasingly complex design process.

The AT&T DSP IDM model simulated the DSP instruction-set with clock-phase accuracy at the model pins. The resulting accuracy of hardware verification allowed us to model the CSP with the entire wireless system. Using hardware/software co-simulation in ATTSIM, we verified the DSP-CSP software interactions in the actual system environment for long simulation times. System simulation speeds with ATTSIM were extremely fast, between 5,000-10,000 DSP instructions per second.

The simulation environment of the DSP IDM model also had the full capabilities of the DSP1618 software and hardware development system. We were able to single step through DSP program execution, set breakpoints, display the values of registers, and view program and data memory contents. Through the simulator memory interface, the IDM instruction set simulator debugger also displayed the values of DSP memory-mapped registers residing in peripheral chips such as the CSP.

Using the DSP 1618 debugger in the hardware development mode, this simulation environment provided a virtually seamless development path from software to hardware breadboard development. We were able to execute the same system-level tests developed during the design on the actual hardware development system with the chips in place. This eased the transition from design to test and made it possible to ramp-up production very quickly.

Conclusion The size, performance, and complexity of mixed-signal chips have grown hand-in-hand with a demand for faster times-to-market and lower production costs. Although the need for change in mixed-signal simulation has been apparent since the late 1980's, it is even more compelling today. Hardware/software co-verification, and a fast and accurate methodology based on a common design, verification, and debugging environment, have become imperative for successful mixed-signal design.

ATTSIM meets these new design constraints. For the CSP1088, using ATTSIM resulted in lower development costs and a faster time-to-market--all while simulating the entire chip accurately on first-pass silicon. The design and verification environment is currently extended to include support for VHDL hardware-software co-simulation using the MTI VSIM/ATTSIM, Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys VSS, and Vantage VHDL simulators to allow VHDL functional modeling and verification of AT&T's next-generation wireless designs. *

Lawrence A. Rigge is engineering director of wireless IC design at AT&T's Microelectronics division (Allentown, PA). He has been involved in the design of DSPs since joining the company in 1985.

Steve Vandris is the technical manager responsible for IC design methodology in the Wireless & Multimedia Laboratory of AT&T Microelectronics (Allentown, PA). Previously, he was a member of the technical staff in the Computer-Aided Design Laboratory (Murray Hill, NJ).

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integrated system design  April 1996