Partitioning System Designs

The tools and methodologies Megatest used to develop the latest high-performance tester.

by Jacobo Bulaevsky and Thomas Iddings

Partitioning on systems such as VLSI integrated circuit testers is not simple. There is a myriad of inter-related but conflicting issues to consider. The proper use of analysis tools to gain confidence in the architecture and partitioning process is crucial. The design of a VLSI IC test system at the Megatest Division of Teradyne Inc. (San Jose, CA) illustrates this point. The system contains a mainframe and high-speed test-head electronics. Analyzing the signal flows between these two components and the different tradeoffs helped determine optimum board, backplane, and component design.

The following were requirements for the development of the Vega system:

Figure 1. The waveform formatter produces very accurate timing signals that are used to control the drivers in the pin electronics board.

Critical subsystems in the Vega system Four critical items were identified very early in the design of the Vega system. These items were the pin support (PS8) card, pin electronics (PE) card, MLA card (which contains the master clock generation and distribution), and cables from the pin support to test-head card cages.

Cable location and type has a major impact on cost, accuracy, signal fidelity, and overall performance. For the Vega system, location of the waveform formatter circuitry and the accuracy of the cables were critical to design success. The waveform formatter takes in the data out (DO), data high (DH), and data low (DL) signals and produces the drive polarity (DP) and drive enable (DE) live signals (see Vega system description and Figure 1). The three signals control the driver as it switches the signal between voltage high (V _ih ) and voltage low (V _il ). This, in turn, provides stimulus to the device under test (DUT).

Other issues that play a significant role based on location of the formatter are the number of cables, size of the test head, and cooling in the test head. In the Vega system, keeping the formatter as one of the last pieces in the PS8 board was most cost effective. From here, the signals were launched, with very accurate timing over long cables, out to the test head and into the pin electronics. The critical items were defined first, and the rest of the system was defined to work with the critical items.

Brainstorming through the different partitioning proposals Before real architectures and specific partitioning proposals emerge, a myriad of tradeoffs need to be considered to formalize the top-level system requirements.

Figure 2. Signal distribution from PSI to PS8 boards. This chart shows results from the embedded isolation resistors' simulation in the pin support backplane.

One tradeoff was the compression of the test vectors. A tester using uncompressed test vectors would be prohibitively large and expensive. In the Vega tester, the vectors get compiled into a highly compressed format. At load time, the vectors get uncompressed on-the-fly through the hardware and combined with timing and waveform information. Partitioning a task between software and hardware is an example of how system size and cost were reduced.

Bus distribution to the eight PS8 boards through the pin support card cage backplane also needed to be defined and verified during system partitioning to have good timing margins and clean data transfers.

One alternative was doubling the number of signals on the PSI board and decreasing the signals' speed, transferring them to the PS8 boards and combining the signals to restore the originals. A second alternative was the use of differential signals that have much larger noise margin. In either case, the number of receivers on the PS8 boards would double, and the PS8 boards would need a higher pin count connector. Another solution was to use embedded isolation resistors in the backplane to make the signals settle faster. This had to be simulated with Spice to make sure that it would adequately handle the issue. The problem with the embedded resistors was that it was relatively new and had its associated risk. Spice was primarily used to analyze signal integrity and settling time. It was also used to fine tune the placement of the isolation resistors and its optimal value. The Spice output (see Figure 2) shows the signal at each of the receiving loads in the chain of PS8 boards. The area outside the keep-out box was defined as the area where the signals should transition and settle. The team decided to go ahead with the embedded resistors solution after all cases were analyzed with Spice.

Another issue is the number of broadcast (BCST) boards in the system. These boards distribute signals from the test support (TS) card cage to multiple PS card cages through high-performance cables. The BCST boards reformat the data for 100-MHz data transfers. The different alternatives are shown in Figure 3. The issues considered in the tradeoff were (1) the number of BCST boards; (2) the amount of circuitry and density in the BCST board versus the PSI boards; (3) the number of interface signals and size, density, and cost of connectors; (4) length of cables; (5) cost; and (6) the load on the drivers that feed the BCST board. Driver load impacts the integrity and settling time of signals. One of the goals was to eliminate any risks with the BCST board, and it was relatively easy to eliminate the complex issues from this board to make it a straight forward design. The decision was, after the signals feeding the BCST board were modeled with Spice, to spread it over 6 BCST boards and divide them up into pairs (see Figure 3d). Spice was used to simulate some of the proposals by building circuits that represented the different topologies. The simulation circuits used models for all the required elements--drives, loads, and transmission lines--and allowed us to feel comfortable with the final decision.

Validation of Vega system Extensive functional simulation was done on all the new ASICs and boards. The tools used for the functional simulations were RapidSim, Verilog-XL, and OpenSim from Cadence Design Systems Inc. (San Jose, CA). OpenSim is a simulation backplane that allows RapidSim and Verilog-XL modules to execute concurrently. The simulations were done by creating elaborate testbenches that exercised the designs through very rigorous sequences of functional vectors. Vector sets were extracted, whenever possible, from actual programs that run on the Vega system or from outputs from other simulations. In most cases, estimated wire delays were extracted from the printed circuit boards (PCBs) after the layouts were completed to have meaningful and realistic timing in the functional simulations.

Figure 3. Different BCST to PSI board communication alternatives were evaluated during the Vega system partitioning phase. In all cases, each PSI board drives 10 PS8 boards for a total of 120 PS8 boards per system. The first configuration consists of 4 BCST boards, 3 PSI boards per BCST board, and 10 PS8 boards per PSI board, for a total of 120 PS8 boards per system (see Figure 3a). The second configuration has the same number of boards, but the bus scheme is completely different (see Figure 3b). Instead of a common bus between the BCST and PSI boards, it has dedicated connections from each of the BCST board to its 6 corresponding PSI boards, and the bus feeding the BCST boards is divided into two. The third option considered shows again a common bus feeding 6 BCST boards with 2 PSI boards per BCST board (see Figure 3c). The last option is similar to the one in Figure 3b where the incoming bus to the BCST board is divided into two, and there are dedicated connections to each of 4 PSI boards (see Figure 3d).

The size and complexity of the system made it impractical to perform a system-level simulation of the entire system. The solution was to combine major blocks from across the entire system into a 2-pin tester slice model that included the complete clock distribution and all of the pipelines. Additionally, some of the structural schematics were replaced with behavioral Verilog for greater simulation efficiency. Since timing is such a critical issue, very precise analog timing was annotated into the functional simulation. Delays for bus signals were extracted from Spice simulations, Motive calculations, and cable delay specifications.

The system-level simulation provided a front-to-back verification across the entire system, while the subsystems' verification tests provided additional coverage. In fact, the system-level simulation uncovered several problems in ASICs that had not been detected through the ASIC-specific simulations.

Because of their critical timing requirements, most of the Vega boards were checked using XTK and Motive tools, both from Viewlogic Systems Inc.'s Quad Design Group (Camarillo, CA). The methodology followed was "design it to be robust, and use the tools for confirmation." XTK was used to do crosstalk analysis and to extract accurate trace delays from the PCB layout. This tool allowed us to find and eliminate problems such as excessive coupling among signals, missing, misplaced or incorrect terminators, trace impedance mismatches, etc. Motive was used to check for worst-case setup and hold timing violations using logic timing models for all the parts in the board. Motive was first used to verify placement using Manhattan-based estimated wire delays. These delays worked very well because the majority were within 5 percent of the actual final route delays. On critical boards, Motive was run with accurate trace delays extracted with XTK. In either case, knowledge based input (KBI) files had to be put together for Motive to describe design-specific information, such as the clock relationships and the multi-cycle paths. On the most critical board--the MLA, with clock frequencies of 200 MHz and 7 different clocks--two problems were detected. One of the problems would have resulted in non-trivial rework. These simulation gave us objective evidence that the design was robust under worst-case timing conditions and ready for PCB fabrication.

Iterative redefinition of a subsystem Originally, the MLA was assigned three functions: master clock generation, logic error catch, and auto calibration. During implementation, it became apparent that the circuit functions would not fit. Alternatives considered included changing the requirements, splitting the circuit functions into two boards, and implementing some of the functionality in new GaAs ASICs. Given that there was a spare slot in the same card cage, the alternative chosen was to split part of the design into a newly defined autocalibration (ACAL) board. With the additional spare real estate, more functionality was added in the ACAL board.

As the design of the MLA board continued, separating the master clock functionality from the logic error catch into another board was considered again to reduce board density. However, the master clock and logic error catch were surprisingly tightly coupled; therefore, a new ASIC was designed. The addition of the new ASIC to the MLA board solved the density problem and again enabled us to add more functionality. It proved to be wise to leave spare slots in the initial definition of the card cages.

Conclusions The Vega system met the objectives in terms of how the system was partitioned, and the integration of the subsystems went smoothly. The key challenges in the final product release were restricted to ASIC vendor issues and problems where full simulation was not possible. A complex architecture problem uncovered during system integration suggests an even higher system-level simulation on the next-generation system design.

Future system-level simulation will be architected to run more efficiently, through the use of more high-level behavioral models, and to access the same simulation models used by the boards' and ASICs' simulation. It is important as the low-level designs get refined that the assumptions made when doing the system partitioning get verified at the system-level in a simple regression test.

Tools, such as Quad Design's XTK, that were used in this design should be directly integrated into the board layout tool--in this case Allegro from Cadence. This would speed up analysis considerably. In the area of worst-case static setup timing analysis, Motive produces very accurate results; however, the process of supplying knowledge based input and extracting the real errors from the problems reported by Motive can be too laborious and needs to be improved.

Jacobo Bulaevsky is EDA manager at the Megatest Division of Teradyne Inc. (San Jose, CA).

Thomas L. Iddings is an electronics engineering consultant who specializes in high-speed clock and data distribution systems with ECL Advantage Inc. (Sunnyvale, CA).

Vega system description

The Vega VLSI IC tester, is a complex, high-speed tester that incorporates a wide range of subsystems and technologies. It consists of large analog and digital sections as well as electro-mechanical subsystems. These contain TTL and ECL glue logic; FPGAs; and CMOS, ECL, and GaAs ASICs. Under computer control, the Vega system provides stimulus to the device under test and compares the DUT's output to a stored known-good response. The figure shows a simplified block diagram of the Vega system. The system contains two major buses as well as critical high-performance cables that connect all subsystems. The major subsystems consist of the tester controller (TC) or host computer; the mainframe (MF), which consists of the test support (TS), pin support (PS), test head support (THS) subsystems; and the test head (TH), where the DUT is loaded. The pin support and test head subsystem uses a true tester-per-pin architecture; thus, each pin can have completely different stimulus within the same vector. The user creates the desired set of test vectors, timing conditions, and electrical conditions for each pin. Compiled into a highly compressed format, the test vectors merge stimulus and response data with timing and electrical conditions to generate the stimulus and response waveforms. The controlled stimulus and response sequencer loads and accesses timing and waveform tables and decompresses and reformats the test vectors as it sends them to the test head. The pin electronics (PE) produces very precise, high-quality signals to drive the DUT, and then senses and returns the response to the mainframe. The mainframe compares the actual and the expected response to determine if the test passed and detects any vectors producing errors. All of these operations occur at 200 million test vectors per second, with the tester accurately placing signal edges within ±150 ps. Simplified block diagram of the Vega VLSI Tester

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integrated system design  August 1996