TOOLS AND TECHNOLOGIES

Products and services for system design

Ethernet controller LG Semicon America (San Jose, CA) has announced a new Ethernet Controller with an on-chip, 16KB SRAM. The GM82C910 is a single-chip solution for IEEE 802.3 Ethernet applications. In addition to the on-chip SRAM, the device also integrates CSMA/CD, ENDEC, ISA bus interface, and a 10Base-T transceiver. LG Semicon America, San Jose, CA. Contact (408) 432-5000.

Maxwell Strata Ansoft Corp. (Pittsburgh, PA) released a new design tool for RF and Microwave designers, called Maxwell Strata. Strata is able to solve for s-, y-, and z- parameters and radiation for 2D, 2.5D and true three-dimensional traces and structures. Seminars to introduce Strata are scheduled for Q1 1996. Stand-alone pricing is $29,900. Ansoft Corp., Pittsburgh, PA. Contact (412) 261-3200, SIinfo@ansoft.com or http://www.ansoft.com/SI/Strata .

Design Desktop for Windows OrCAD (Beaverton, OR) introduced new releases of OrCAD Capture, OrCAD Layout, OrCAD Layout Plus as well as new products, OrCAD Layout Ltd. and Design Data Link for Capture, for its Design Desktop for Windows. All products are run as native 32-bit applications in Windows. In addition, OrCAD announced OrCAD Simulate for Windows , a simulator targeted specifically for verifying logic and timing of CPLDs and FPGAs. OrCAD Capture is $995, Layout is $4,995, Layout Plus is $9,995, and Layout Ltd. is $1,995. Design Data Link has an introductory price of $250, and Simulator for Windows is $2,495. All products are available immediately. OrCAD, Beaverton, OR. Contact (800) 671-9505 or info@orcad.com .

User programmable gate array Crosspoint Solutions (Milpitas, CA) unveils a family of very fine grained programmable gate arrays with from 20,000 to 100,000 usable gates. The array structures map well into the ASIC design flow with HDLs and synthesis, and can achieve system speeds of over 100MHz. The internal cell structure employs a super-fine grained half-gate basic building block called a CoreCell. Two CoreCells can be arranged to form a 2-input NAND or a latch. The front-end design is accomplished through standard tools. The back-end design suite, called the ASIC++ Design System includes Cross Examiner, Design Floorplanner, Timing Driven Place and Route, and Time Checker. Crosspoint Solutions, Inc. Milpitas, CA. Contact (408) 324-0200.

Full system mixed-level simulation Alta Group of Cadence Design Systems, Inc. (Sunnyvale, CA) announces Convergence Simulation Architecture based on UC Berkeley's Ptolomy project research. The tools facilitate the development of virtual prototypes which can include models of the environment by working with full-system, mixed-level, and mixed-domain simulation. Available January 1996 at $25,000 per seat. Multimedia Design System In addition, the Alta Group announced the Envision Multimedia Design System. This new package is the first to address convergence applications, those that combine communications, images, and sound. Alta Group of Cadence Design Systems, Inc. Sunnyvale, CA. Contact: Steven Glaser (408) 733-1595 http://www.altagroup.com/

Formal verification Chrysalis Symbolic Design (Billerica MA) unveiled its Design VERIFYer 2 software for formal verification. Design VERIFYer 2 handles the complete design flow from RTL through gates to transistors. It accelerates design of complex ASICs and microprocessors by providing fast, thorough verification of design revisions. Design VERIFYer 2 is available now for $95,000. Chrysalis Symbolic Design, Inc. Billerica, MA. Contact (508) 436-9909.

Logic emulator Virtual Machine Works (Cambridge, MA) introduced a lower cost logic emulator designed for better performance and ease of use. The VirtuaLogic Emulation System permits use of existing Verilog debug and analysis tools. The system can simultaneously handle multiple or gated clocks and asynchronous logic. The VirtuaLogic Emulation System includes the VirtuaLogic Compiler and VirtualProbe Analyzer software modules and the VirtuaLogic Emulator. Prices start at $125,000 Virtual Machine Works, Cambridge, MA. Contact (617) 621-1700.

Fast deep submicron simulator Anagram (Sunnyvale, CA) unveils ADM 2.0 simulator. The transistor-level simulator provides 10X to 1000X speed improvement over SPICE for large memory and logic circuits and 10 to 100 speed improvement for analog and mixed-signal circuits for deep submicron timing and power simulation. List price is $55,000. Anagram, Sunnyvale, CA. Contact (408) 720-7400.

PC parallel port ASIC Shuttle Technology (Fremont, CA) has debuted an Enhanced Parallel Port EPEZ ASIC. The single chip solution interfaces a PC's parallel printer port with any IDE bus-capable peripheral such as 8/16 bit IDE disk, ATAPI-CD and ATAPI tape. The chip allows direct memory access without needing additional software. Shuttle claims a 40 percent performance boost over competitieve devices. Shuttle Technology, Inc., Fremont, CA. Contact (510) 656-0180.

RTL floorplanner High Level Design Systems (Santa Clara, CA) introduced Top-Down Design Planner. Top-Down DP is a deep submicron floorplanner that uses unique HDL estimation and analysis technology to map HDL code to physical blocks. Unlike existing tools that require completion through synthesis before timing is extracted, Top-Down DP extracts physical layout-based information and gate-use statistics from the HDL. Since the tool maps HDL code to physical blocks, Top-Down DP can check intra- and inter- block layout dependent timing, and automatically generate "black-box" timing models of nested blocks. The tools permits the designer to evaluate the logic, timing, and power consumption at the RT level where the largest changes are possible. Pricing starts at $65,000. High Level Design Systems, Santa Clara, CA. Contact (408) 748-3456.

Area router Cadence Design Systems (San Jose, CA) introduced Silicon Ensemble, an advanced suite of area-based place and route tools. The tools include FlexChip Optimizer, Universal QPlace+, application-specific optimization, Advanced Interconnect Analysis, and FlexChip Manager (a Windows type GUI that simplifies the design process and improves layout productivity for deep submicron designs). The Silicon Ensemble includes library and intellectual property importation and generation facilities that improve P&R efficiency through design reuse. Pricing starts at $265,000. Cadence Design Systems, San Jose, CA. Contact 1-800-PHONCAD or cadenceconnect@cadence.com

integrated system design  February 1996