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TOOLS AND TECHNOLOGIESProducts and services for system design
Polygon compactor Segantec and their US distributor Technical Data Freeway have added new features to the Design Rule Enforcer & Manager (DREAM). The polygon compactor and optimizer now provides full 45 degree compaction and intelligent autojogging. The tool also improves splicing for compaction of regular structures and a new abutment rules format that allows processing of more complex structures. Another new capability allows the designer to recontact source-drain contacts for more layout compaction. The tool also contains new properties with design rules such as compacting only x or y and size extend x or y, as well as Manhattan versus diagonal compaction. Technical Data Freeway, Concord, MA. Contact Fred Hinchliffe at (508) 371-9004. Quick test benches Chronology .com/quickbench/isdpromo.html&lf=isd-sendtolog"> Chronology introduced QuickBench, a product that automatically generates self-checking testbench models exclusively from intelligent timing diagrams. Based on TimingDesigner, QuickBench produces VHDL and Verilog testbench models used to verify designs during simulation. QuickBench models are used during an HDL simulation to stimulate the inputs and automatically respond to the resulting outputs, reporting errors as necessary. This is done by surrounding the design under test with an "intelligent" layer of HDL code that models the rest of the system. QuickBench creates self-checking models that respond to the design under test. It is available immediately on HP and Sun workstations. It is also available for PCs running Windows 3.x, 95, and NT. It is priced at $15,000. Chronology Corp., Redmond, WA. Contact (206) 869-4227. Cycle-based simulator SpeedSim announced Version 2.0 of its high-performance SpeedSim/3 cycle-based simulator. This version supports RTL design input. The addition of Verilog RTL constructs allows design engineers to use cycle-based simulation at the front end of a project to speedup simulation. The company claims SpeedSim/3 2.0 can compile a Verilog RTL design with 1 million equivalent gates in under 15 minutes. Version 2.0 compiler and User Interface will accept design files with any combination of Verilog RTL and gate-level primitives that compile directly into Native-Code for the SpeedSim/3 Boolean Data Flow Engine. The US list price for Version 2.0 of SpeedSim/3 is $35,000. SpeedSim Inc., Westford, MA. Contact (508) 692-3737. Multi-purpose codec Analog Devices announced AD1843 SoundComm codec. It supports up to four simultaneous sample rates, allowing it to synchronize and unify audio, modem, fax, and video signals. The device addresses the need for a single, low-cost audio and communications front end in PCs where sound cards, fax/modems, multimedia, and telephony applications are converging. The codec gives add-in card manufacturers a way to combine, on one card, a wide range of sound, fax, and modem functions that can run concurrently. It also brings PC makers a step closer to adding these functions directly to a motherboard by providing a multimedia front end for host-based signal processing designs. The unit price in quantities of 1,000 is $15.00. Analog Devices Inc., Norwood, MA. Contact (617) 461-3881. 100BaseTX transceiver Silicon Systems now offers a single-chip, mixed-signal 100BaseTX fast ethernet transceiver for 5.0- and 3.3-V operation. The 78Q2121 transceiver only requires isolation transformers, a 25MHz crystal, and a few passive components to implement a complete 100 Mbit/s Ethernet link over standard Category 5 unshielded twist pair cables. Available in 48-lead TQFP packages, the 78Q2121 are available off-the-shelf for $25.00 each. Silicon Systems, Tustin, CA. Contact (800) 624-8999 x151.
integrated system design April 1996[ Articles from Integrated System Design Magazine ] [ ICs and uPs ] [ Custom ICs and Programmable Logic ] [ Vendor Guide ] [ Design and Development Tools ] [ Home ] For more information about isdmag.com e-mail cam@isdmag.com For advertising information e-mail amstjohn@mfi.com Comments on our editorial are welcome. Copyright © 1996 - Integrated System Design Magazine |
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