TOOLS AND TECHNOLOGIES

Products and services for system design

Gate array Microchip Technology (Chandler, AZ) introduced the QuickASIC gate array family, which can replace standard FPGAs and CPLDs with a masked ASIC. Microchip's QuickASIC family offers turnkey digital design conversion of any FPGA/CPLD device by transforming its netlist into a masked ASIC--with very fast lead times of less than four weeks from design signoff to prototypes. QuickASIC devices provide drop-in functional pin-for-pin replacement of FPGAs/CPLDs; seven array sizes ranging from 2 to 84 kgates; 84 to 304 pads offering completely user-definable pin-outs; fewer than 7 ns typically (from input through a flip-flop to output); and 2.7- to 5.5-V operation. The company's Zero-NRE program eliminates the NRE costs charged by traditional ASIC manufacturers and includes one free design turn. QuickASIC will support all popular packaging types, including SOIC, PLCC, PDIP, PQFP, TQFP, and VQFP. Available today in 5,000-piece minimum quantities, pricing for QuickASIC ranges from $4-6 per device for 2 kgates to $20-28 per device for 84 kgates. Microchip Technology Inc., Chandler, AZ. Contact (602) 786-7200.

Formal verification Compass Design Automation (San Jose, CA) announced Verilog capabilities for their VFormal formal verification tool. Now designers can verify their code in their choice of Verilog, VHDL, or a combination of the two languages, all running on a single verification engine. In addition, Compass introduced Laybool, a tool that creates functional Boolean VHDL or Verilog directly from transistor netlists. The combination of tools allows designers to perform direct layout versus RTL in a formal verification environment. Pricing for VFormal is $60,000 for either Verilog or VHDL and $120,000 for the mixed-language environment. Pricing for Laybool is $95,000. Compass Design Automation Inc., San Jose, CA. Contact (408) 433-4880 or www.compass-da.com.

Full-chip extraction Avant! (Sunnyvale, CA) announced the availability of Star-R version 2.0, a full-chip Smart Extraction package for deep submicron IC designs. Star-R version 2.0 extracts full-chip accurate parasitic information and signal delays to within five percent of actual chip implementation. Complex designs with more than 20 million transistors can be analyzed. Star-R also includes fast RC circuit reduction with accuracy control and asymptotic waveform evaluation (AWE)-based simulation for accurate interconnect delay calculations. The extracted parasitic and signal delay information is generated in industry-standard formats and is ready to be used by logic and timing simulators. Complex clock distribution networks and critical signals can be extracted and analyzed easily with Star-R's graphical analysis capabilities. Star-R version 2.0 is available immediately. U.S. pricing starts at $125,000. Avant! Corp., Sunnyvale, CA. Contact (408) 738-8881, info@avanticorp.com, or www.avanticorp.com.

NT workstation Digital Equipment (Maynard, MA) announced new Pentium Pro-based Windows NT personal workstations. The new workstations are available as single and multiprocessor deskside systems. The workstations feature 180 or 200 MHz Pentium Pro processors, up to 256 Mbytes of EDO RAM, 256 kbytes internal cache, PCI bus, and a range of 3-D graphics options. The Personal Workstations can be upgraded to use the 64-bit Alpha processor. The Personal Workstation Model 200i, fully configured, is priced at $5,372. The Model 180i is priced at $3,697, and the Model 200i2, with dual 200 MHz processors, is priced at $4,751. Digital Equipment Corp., Maynard, MA. Contact www.workstation.digital.com.

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integrated system design  November 1996