TOOLS AND TECHNOLOGIES

Products and services for system design

Microprocessor for Java Sun Microsystems unveiled its JavaChip silicon. Sun claims the picoJava I microprocessor core is an efficient Java execution unit design that is expected to deliver up to 20x the Java performance of X86 and other general-purpose processor architectures, as well as up to 5x the performance obtained by just-in-time (JIT) compilers. The picoJava I architecture consists of a RISC-style pipeline with a Java byte-code instruction set. It can be configured with or without a floating point unit and up to 16 kbytes each of instruction and data cache. It can also be implemented in a variety of CMOS processes. Preliminary versions of the picoJava I core specification and core simulator are available today. The picoJava I core design kit is scheduled for availability by the end of Q1, 1997. Sun Microsystems Inc., Mountain View, CA. Contact Paul Karr (415) 961-1551, pkarr@kvo.com, or www.sun.com/sparc.

ASIC Samsung Semiconductor introduced the first in a new family of deep submicron ASICs. The EDL60 has 60 kgates of random logic and 1 Mbyte of on-chip DRAM. Future additions to the family of devices will eventually extend to 400 kgates and 16 Mbits of embedded DRAM. The ASIC family is aimed at high-integration applications such as set-top boxes, digital video disk (DVD) systems, interactive video games, Ethernet/ATM switches, graphics/MPEG frame buffers, and on-chip cache for CPU subsystems. Specific pricing is dependent on product complexity and architecture. Samsung Semiconductor, San Jose, CA. Contact (800) 446-2760.

Simulator upgrade Viewlogic Systems introduced the Chronologic VCS 3.1 simulator, a faster gate-level version of its RTL-level Verilog simulator. According to Viewlogic , the VCS 3.1 runs 2x to 5x faster than VCS 3.0, and it improves gate-level simulation speed by optimizing timing models on a global basis, rather than instance-by-instance. VCS 3.1 is a maintenance upgrade to VCS 3.0. The Unix-based version is available today, and the Workview Office version (Windows-based) will be available later in Q4 of 1996. Viewlogic Systems Inc. , Marlboro, MA. Contact (508) 480-0881, fax on demand at (800) 443-8533, or www.viewlogic.com.

EEPROM family Microchip Technology launched the 25CXXX Serial EEPROM family, which supports the Serial Peripheral Interface (SPI) bus. The 25C080/160 provides 3 MHz maximum bus rate, a 16-byte page buffer, and hardware- and software-enabled write protection features with the ability to write protect user-selectable portions of the memory array via software. These devices offer 10 million erase/write cycle performance, data retention of more than 200 years, and ESD protection of greater than 4,000 V. The 25C080/160 devices are available in PDIP and SOIC packages. Pricing in 1,000 unit quantities is $1.08 for the 25C080 and $1.34 for the 25C160 (commercial temperature PDIP versions). Microchip Technology Inc., Chandler, AZ. Contact Keith Pazul (602)768-7458.

Processors benchmark Berkeley Design Technology announced a study that benchmarks the digital signal processing (DSP) capabilities of general-purpose processors, including the Intel's Pentium, IBM/Motorola's PowerPC 604 and 604e, Advanced RISC Machines' ARM7, and Hitachi's SH-DSP. The study also projected performance for the Intel Pentium with MMX extensions. "DSP on General-Purpose Processors" is priced at $2,500 for initial copies and will be available in late December. Berkeley Design Technology Inc. Fremont, CA. Contact Garrick Blalock (510) 791-9100, dspgpp@bdti.com, or www.bdti.com.

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integrated system design  December 1996