Viewpoint

Defacto Standards Set the Pace­A Life-Cycle

Standards work best when they are based on existing installed technologies.

by Andy Graham

The EDA industry is in a virtual alphabet soup of standards and standards bodies. A good deal of this confusion stems from the origin of the standards. Many of these efforts were initiated by EDA vendors seeking to gain a market advantage. But users have also been active in promoting standards such as CFI and EDIF.

Why aren't standards producing better results? Often, the adoption of a standard is influenced by its source and the support it receives. Both Verilog and VHDL were standards long before organizations were formed to promote them. In contrast, VITAL, OMF, and even CFI's DR are catching on at a much slower rate.

Standards work best when they are based on existing installed technologies. These technologies tend to be closest to the "whole product" of the standard. Probably the most successful contemporary example of this is Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys ' early decision to synthesize Verilog and output EDIF netlists. In the following, we will use synthesis to illustrate the phases of a standard's life-cycle:

Innovation In the early stages of technology development, chaos occurs when a number of solutions are tried and discarded, making the definition of a standard risky. The risk correlates to the number of possible winning approaches that lead warring entrepreneurial engineers to concede territory to exploit the core technology and not its supporting architecture. In short, it is too early to standardize. Current examples are formal verification and behavioral synthesis language.

Standardization This stage is entered when innovation slows, so the number of possible choices and attendant risks are known. In 1986, four companies announced synthesis products at DAC. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys was the only one that directly parsed Verilog, making it a drop-in solution for hundreds of Verilog users. Synopsys .com/isdweb/&lf=isd-sendtolog"> Synopsys was destined to take the checkered flag even though its competitors may have had superior algorithms. Silc and SCS violated a marketplace rule by betting on the superiority of their algorithms without regard to a decision already made by the market. This is the same scenario for a submicron delay calculation solution. CFI has been engaged by ASIC vendors to transfer the IBM-developed Delay Calculation Language and its compiler as a defacto standard.

Maintenance to end of life Even for the successful standards such as Verilog and VHDL, problems persist in the consistency of their implementation. It is difficult for either HDL to produce identical results across multiple simulators. Simple formats such as the Standard Delay Format (SDF) exist in multiple versions across tools, and EDIF interoperability problems are legendary. In some cases, the EDA industry will have legitimate difficulty supporting conflicting standards and should decide to end support or, at least, stop further development of standards in some areas.

Will EDA fix the standards problem? Not unless all the leading vendors play the standards game by the same rules and proactive leadership prevails over reaction/spin management. I've heard insanity defined as "doing the same things over and over again while expecting different results." We at CFI believe that defacto standards will lead the way­with long-range planning via the roadmap process, and managing the standard's life-cycle being the best way to "fix" the problem.

Andrew J. Graham founded CFI, Inc. in 1988 and is currently the chairman and president of the company.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  January 1996