Viewpoint

The Era of the Mini-Methodology Current tools do not address all of the deep submicron issues. by Simon Napper

Market demand for deep submicron silicon ensures that most design starts are for process geometries of 0.5 µm or below. Unfortunately, the required methodology and tools are not always available. Designers struggle through challenges without help from techniques and tools that are designed specifically to deal with deep submicron problems. Finding solutions is often bewildering and it's tempting to simply plug holes. The struggle for solutions is exacerbated by so many point tools to plug these holes.

A better starting point is to examine the methodology for design. Deep submicron forces an evolution in methodology that changes the design landscape. Existing methodologies came from approaches that are dated. They were not intended to manage the level of complexity and sophistication designers now deal with.

Any methodology is a set of steps to ensure designs are thoroughly planned and rigorously checked. As the designs have become larger and more complex, so have methodologies. For success with deep submicron, design methodology must change from being a large, complex monolith of steps to a set of smaller, simpler mini-methodologies that interact. This enables a "divide and conquer" approach to managing complexity and provides flexibility for handling a diverse set of design elements. The tradeoff is more complex interfacing between mini-methodologies to ensure the overall methodology is secure. Of particular interest are full-chip verification and analog-digital block interaction.

Tools automate specific steps and solve specific problems. There is a growing "design crisis" from designers' inability to exploit silicon capability. Designers are looking to the EDA community for tools that enable the designers to meet the productivity-accuracy gap which has recently opened up.

The gap has become quite obvious in certain areas. RC extraction and manipulation is essential for accurate prediction of IC performance. SEMATECH stated that design performance will be 70% dependent on interconnect delay. Without accurate extraction, performance prediction amounts to guesswork. Low-power design and analysis capabilities are essential to support the dramatic growth of nomadic products. Add to this the reliability benefits from reduced current flow. Mixing gate, transistor and RTL analysis enables full chip simulation across multiple levels of design. Structured-custom demands both gates and transistors. The RTL link will boost productivity by allowing faster simulation of well characterized blocks. Mixed-analog and digital simulation becomes essential to check phase-locked loops and other analog blocks appearing on many designs. Designers cannot simply guess at the interaction between the digital and analog blocks.

The relationship between tools and methodology is complex. Ideally, designers want tools that automate and enforce methodology. Pragmatically, designers often forge methodology using whatever tools are available.

The IC design community has been very successful at overcoming new technology hurdles as new silicon processes emerge. Deep submicron is the next chapter in this continuing conquest of electronic systems. By first looking at the methodology that is appropriate, the users will sort out priorities that will lead to continued success designing deep submicron ICs.

Simon Napper is vice-president of marketing for EPIC Design Technologies.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  February 1996