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ATG Arrives in ASIC Design Test generation tools require new approaches for large IC designs. by Ralph Marlett

Automatic test generation (ATG) for sequential circuits is generally recognized as one of the most difficult tasks in EDA. In the 80's, when such tools first came on the market, customers did not believe that sequential ATG was feasible. Sales presentations had to start with simple examples of test generation algorithms to convince the customer that such a tool was possible.

Since that time, many EDA suppliers recognized the testing problem their ASIC customers faced and the business opportunity it created. Unfortunately, underlying tools often lack the technical depth to deal with even modestly complex designs. Though these products are offered as sequential ATG, they primarily focus on full scan with limited ability as sequential circuit test generators. Their partial scan methods often require testability overkill because of their inherent weakness in test generation and the imprecise means used to select scan locations. In some cases, these methods require over 80 percent of the flip flops to be scanned.

In 1975, Ibarri and Sahni proved that ATG for combinational circuits was in the class of NP-complete problems. This means that in the worst-case situation, complexity of test generation grows at least as an exponential function of circuit size. Many EDA developers seemed to have interpreted NP to mean "not possible" because recent efforts have shifted to less ambitious solutions. For example, design or test rules checkers are now commonplace. However, their real purpose is to compensate for the tool's lack of algorithmic horsepower by filtering out complex but frequently necessary design techniques like derived clocks and asynchronous signals. IDDQ testing has been a hot topic in recent years. Twelve papers were devoted to this topic at the 1995 ITC. BIST has also re-emerged as a possible solution by shifting the test generation problem to a design problem. These and other novel techniques should be viewed as complementary to sequential ATG rather than as universal replacements.

Experience has shown that automatic test generation performance is maximized when combined with an effective design for testability method. Full scan is certainly a proven method, but for many ASICs where routing or performance is critical, partial scan methods linked to a sequential ATG may provide the only acceptable solution. As test generation and the means to select scan locations become more powerful, the amount of scan is reduced while maintaining high fault coverage.

IDDQ, BIST, and various other methods have practical application and will continue to benefit from on-going research, but the cornerstone of an effective testability solution is strong ATG. High-performance automatic test generation eliminates much of the testability logic required by today's tools. Clever scan design techniques, combined with ATG, offer testability improvement without significant performance degradation. Such a combination expands designer flexibility and reduces hardware requirements.

The next quantum leap in testing will come from the integration of ATG tools, designed to accept various functional data, with logic synthesis tools that can derive such data. This would include state machine identification, control signal definitions, and other information that can dramatically improve test generation performance. An integrated ATG and synthesis product could achieve high fault coverage with less design impact than anything available today. *

Ralph Marlett is president and CEO of ATG Technology, Inc. (Ramsey, NJ).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  April 1996