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IC Power: a Hot Problem?

Power consumption is moving to the front of the design agenda.

by Lorne Cooper

What is provoking this sudden concern about power dissipation in IC design? Like many "new problems," IC power questions have been around for a long time; it's the answers that are falling apart. Power dissipation in CMOS ICs has been growing for a decade and doubling roughly every two years.

The effect of increasing IC power has traditionally been more expensive packaging, heatsinks, fans, and larger power supplies. Two factors have made the "package and fan" answer less of a solution: (1) the growth of the battery-powered electronics market, where there is no fan, and battery life is a key ingredient in product profitability; and (2) the non-linear increase in packaging cost per watt dissipated, which makes manufacturing solutions both expensive and late, requiring more development cycles to accommodate package, board, and system-level changes.

Intel's Pentium processor is an example of the change in market sensitivity to power dissipation. While an outstanding success, its high-power dissipation kept the product out of the portable market, allowing 486-compatible manufacturers to compete. Today, Intel is still losing potential customers to lower power PC Notebook processors long after floating-point accuracy questions have been forgotten.

As designers of battery-powered equipment learned long ago, there is no "magic bullet" to solve power issues. IC power management requires the inclusion of power with timing and area, as parameters managed throughout the design process.

Few companies choose an IC process without looking at power efficiency, and power budgets are in virtually every IC specification. However, many design managers finish the discussion of power dissipation at the spec review, waiting for the good or bad news from prototype runs; by then, power issues are hard to fix.

Design reviews are the right time to question implications of design changes on power. Typically, 60 percent of available power savings in an IC design is at the architectural level, before synthesis to a gate-level design. This level is where designers find "low-hanging fruit": deactivating datapath blocks, re-ordering RAM access, and taking advantage of signal correlations. Once the design is fixed by timing optimization and routing, even inserting a few gates can force rework of an entire floorplan. Architectural design-stage goals must include a power budget.

There are now tools available for ASIC and full-custom IC power analysis at many different levels. These include DSP algorithm-, pre-synthesis architectural-, gate-, switch-, and transistor-level tools. Design reviews can include results from power analysis tools at the algorithm and architectural level. Later gate-, switch-, and transistor-level verification tools can preserve power gains and prevent costly mistakes.

Power efficient design is within reach. Management commitment, training, and tools are what make the design process work. Many low-power projects have shown dramatic results from application of power efficient algorithms and timely feedback from design tools. These tools, when motivated by management willingness to ask tough questions about power dissipation throughout the design cycle, focus design teams on power issues. This prevents problems before prototypes come back and the crisis begins.

Lorne Cooper is president of Sente Inc. (Chelmsford, MA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  July 1996