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Future Directions for the Verilog Language The IEEE approved Verilog as a language standard in December of 1995. by Maqsoodul Mannan

As we move from the standardization phase of Verilog to improving and enhancing the Verilog language, we will take care to focus our efforts on not only improving the language and making it easier to use, but also on improving the Verilog design environment. The following new requirements will be addressed by the IEEE 1364 Verilog Standards Group (VSG):

• Compatibility with twenty-first century deep submicron designs.

• System- and architectural-level descriptions.

• Structural changes to accommodate analog extensions.

• Analog extensions to Verilog.

• Inclusion and definition of synthesizable Verilog.

• New extensions to the language in scheduling semantics and specifying blocks.

• Adding extensions to the access (ACC) and Verilog procedural interface (VPI) routines to accommodate all the above.

Open Verilog International's (OVI) technical subcommittees have been working diligently in these areas. It is the intention of OVI and the 1364 VSG to put approved specifications for these new requirements in the IEEE domain in the shortest time possible.

As it stands today, the IEEE 1364 standard should have few problems handling deep submicron designs, but careful review and recommendations are necessary so that the Verilog standard can stay ahead of user needs. In the same vein, we also need to extend the IEEE 1364 standard to include system- and architectural-level constructs and capabilities.

Analog extensions to the 1364 standard are essential for the increasing number of Verilog users worldwide who are doing mixed-signal designs. The current proposal consists of a number of elements provided by different sources. OVI's Verilog-A TSC is working towards ratifying a unified version of all these extensions. The results of their effort will be submitted to the IEEE for its standardization process. Because of their complexity, Verilog's analog extensions may require structural changes to the IEEE 1364 standard.

Up to now, Verilog has been a simulation language without specific synthesis constructs and language extensions. The definition of synthesizable Verilog and its inclusion in future versions of the IEEE 1364 standard are essential to providing a complete design environment.

In extending the language, it is critical to advance the state of the art for Verilog's ACC and VPI routines. As we add analog extensions and architectural- and system-level additions to the IEEE 1364 standard, it is essential to provide for these additions in both the ACC and VPI.

In conclusion, the future of Verilog HDL and the existing investment made by the users is very secure because the language is continually evolving to meet the technology requirements of its users. Existing models and libraries will maintain their integrity, and Verilog tools will remain the best and most comprehensive tools available to support the Verilog users, who have invested more than $25 billion in Verilog over the last decade.

With the opportunities we have to enhance Verilog, we will continue to reap benefits from our investments. We can be secure in knowing that our new technology will reach the market first and with the highest level of quality possible because of our decision to use the Verilog language.

Maqsoodul Mannan is vice-chair of OVI, chair of the IEEE Verilog Standards Group, and he is a Verilog user.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  September 1996