ASIC Technology

3-D Parasitic Extraction for Deep Submicron IC Design

Advances in process technologies have increased the requirements for a more complete analysis of interconnect characteristics.

by Wayne Dai and Weikai Sun

Increasing demand for greater functionality, higher performance, and shorter design-to-manufacturing cycle time in smaller yet faster packaging is driving the design and development of next-generation electronic products. The National Technology Roadmap for Semiconductors projects that by 1998 the feature size will shrink to 0.25 µm, and the chips may contain as many as 28 million transistors. As the width of the wires shrinks, resistance increases more rapidly than capacitance decreases. Consequently, interconnect contributes 50 percent of the total delay in 0.35-µm technology and is expected to contribute up to 70 percent for 0.25-µm technology.

Interconnect delay on the chip dominates the gate delay. A large height-to-width ratio--2 to 1 in 1998 and 2.5 to 1 in 2001--and many interconnect layers make lateral coupling increasingly more significant than coupling to ground. Crosstalk not only causes a wrong logic result during a particular clock cycle, but also leads to a different timing behavior of neighboring lines. Delay cannot be calculated accurately without taking crosstalk into account.

Most methods of design verification use 2-D extraction, which is highly inaccurate when used on deep submicron designs. It cannot model all the 3-D field effects, such as complex capacitive coupling between geometries, and it cannot handle conformal dielectrics or nonorthogonal conductor cross sections. The inaccuracies of 2-D extraction on critical nets for designs using these new technologies will result in many design or mask iterations. Consequently, successful design verification requires accurate 3-D parasitic extraction.

2-D, quasi-3-D, and 3-D parasitic extraction Based on the degree of simplification made, extraction methodologies fall into three categories: 2-D, quasi-3-D (or 2.5-D), and 3-D parasitic extraction.

Two-dimensional parasitic extraction ignores all 3-D details and assumes the geometries being modeled are uniform in one dimension, usually the signal-propagation direction. Take a simple 1-by-1 crossover, for example: 2-D parasitic extraction will model this structure as three 2-D sections with corresponding lengths, two one-conductor cross-sections to capture the two non-overlapping areas for the critical net, and one two-conductor cross-section to represent the overlapping area. All 2-D pieces are treated as though they extend to infinity. The actual parasitic parameters, capacitance, and resistance values are calculated by multiplying their obtained values by their corresponding lengths. This approach is simplest: It divides nets in the most straightforward way and reduces the original structures to a set of 2-D sections. However, this method is also the most inaccurate, as it cannot capture any of the 3-D effects of the original structure.

Quasi-3-D parasitic extraction goes a step further than 2-D extraction. It sweeps any 3-D structure in two perpendicular passes, and by playing with geometry superposition, it can model 3-D structure more accurately. The 1-by-1 crossover, for example, involves two passes--each is a 2-D extraction. By adding the results together and subtracting the overlapping area, quasi-3-D extraction can see some of the original 3-D picture. However, because the process used during the two passes is only 2-D, it cannot model all the 3-D effects.

As its name indicates, 3-D parasitic extraction models all structures in three dimensions. For example, the 1-by-1 crossover is thrown into 3-D parasitic extraction and is modeled as a whole 3-D piece. Therefore, this approach can capture all 3-D effects.

In short, 2-D extraction is fastest but least accurate; 3-D extraction is slowest but most accurate; and quasi-3-D plays the middle ground with moderate speed and accuracy.

Full-chip 3-D extraction vs. selective 3-D extraction The increasingly important role of interconnect makes accurate modeling in 3-D more critical for a successful design. However, it is prohibitively expensive to extract every net in 3-D; in fact, it is not necessary. A multi-tiered extraction methodology is required. Some current standardization efforts, including SEMATECH's Chip Parasitic Extraction and Signal Integrity Verification project, can facilitate the seamless integration between high-capacity 2-D extractors from major vendors and high-accuracy 3-D extractors from niche players.

Figure 1. Decomposition of a net into crossovers with a "big" gap (A) produces negligible error. Some designs, like memories, yield evenly spaced crossovers (B) requiring the use of periodic boundary conditions.

First, any commercially available 2-D extractor can be used to extract simple, lumped-capacitance values for all nets. This information can be used to filter out non-critical nets, based on three factors: length, drive strength, and loading conditions. This step can process up to 300 nets per second with 20 to 40 percent error tolerance. Next, we use the same 2-D extractor to extract distributed RC for the remaining nets. Based on the given timing budget and crosstalk margin, we screen those nets to determine which need accurate 3-D extraction. Nets can be screened at the rate of 10 nets per second, with 10 to 20 percent error tolerance. Most commercially available extractors are adequate for the lumped-capacitance filtering and 2-D RC-screening process. In other words, there is no need to throw away the investment in those tools. The challenge is to deploy a 3-D extractor for the remaining nets. The requirement for the 3-D extractor is 1 net per second on average, with less than 5 percent error tolerance. The percentage of nets needing 3-D extraction increases as the design rules shrink and clock speed increases. Right now it amounts to 5 to 10 percent.

3-D extraction for critical nets From the capacitance filtering and RC-screening process, most of the nets will be handled by rough but efficient 2-D and quasi-3-D extraction tools. The remaining critical nets, however, require more accurate extraction in order to capture 3-D effects.

There are two methods of dealing with this problem. One is to treat the whole critical net and its neighbors as a huge 3-D structure and try to model them all simultaneously. The other approach is to decompose the whole net and its neighbors into many smaller sections, then deal with each one in a 3-D manner.

Full 3-D solution on the whole critical net The idea of the first approach is to throw the whole critical net and its neighbors into some field solvers, either deterministic, such as the finite element method (FEM), or non-deterministic, such as a Monte Carlo integration ("random walk") algorithm. The advantage is that the highest degree of accuracy is achieved in terms of the capacitance and resistance values of the critical net. However, there are many problems with this approach.

First, because the critical nets that require accurate 3-D extraction are typically global signal lines such as global buses and clock nets, the problem domain is usually huge. Therefore, it is computationally prohibitive to run such a large-scale problem in a 3-D field solver. One simplification is to assume planarization to gain the necessary speed, but doing that is at the expense of required accuracy.

Another problem with this approach is the accuracy the final RC netlist it will supply. Obviously, we cannot output a single, huge lumped capacitance for a critical net; we must partition the net to output a distributed RC netlist. Partitioning is required by the subsequent circuit-reduction and simulation tools to guarantee the electrical properties of the interconnect. For deterministic methods such as FEM, distributed capacitance can be obtained by partitioning the net and summing all charges in each small section, an approach that contradicts the initial "no-cutting" belief of the full 3-D solution. Conversely, a non-deterministic approach such as random walk obtains capacitance from an infinite integration without solving a field distribution. It is difficult, if not impossible, for such an approach to output a distributed-RC netlist without any partition of the original interconnects.

Therefore, because of the computational inefficiency and difficulty of generating a distributed-RC netlist, using a full 3-D solution on the whole critical net is not an efficient extraction solution, despite the fact that it can extract the most accurate lumped-RC values.

on-line solvers vs. interconnect library The basic assumption of using a full 3-D solution on the whole critical net is that any partitioning of the original net will destroy the accuracy. In fact, we can get a fairly accurate solution by carefully or intelligently partitioning the net to control the boundary effect for all small sections.

Figure 1 shows multiple crossovers to the critical net capacitance. Figure 1A shows there is a big gap between two groups of crossovers. From our knowledge of field distribution, we know the 3-D field of one group of crossovers will degenerate into 2-D distributions some distance away from the crossover, and this decrease is exponential with respect to the distance between the groups of crossovers. Therefore, we can partition somewhere between the two groups without significantly reducing accuracy. In some dense and compact designs such as memory, however, all nets are routed in minimum spacing, which provides little chance of hitting cases with a big enough gap between two 3-D patterns. Figure 1B, where all crossovers are equally spaced, illustrates this problem. For this kind of structure, we can use special properties such as periodic conditions to partition the net into smaller and simpler 3-D patterns without affecting accuracy. Therefore, by using a carefully thought-out strategy for partitioning the interconnect, it is possible to break the critical net and its neighbors into many smaller and simpler sections with the same accuracy as applying full a 3-D solution to the whole critical net.

Figure 2. Decomposition of a net results in one of a variety of 3-D interconnect patterns, each requiring separate analysis.

But now comes the problem of how to extract each small section. One way is to apply field solvers on-line for each small piece and store the results with the geometry so that we don't need to rerun field solvers when the same structure arises later. If we use exact matching to determine whether a specific geometry has been calculated, it will invoke too many unnecessary runs for similar yet different structures, such as crossovers with the same topology but different spacings. If we use the closest match instead of an exact match, we lose accuracy because we have essentially changed the geometry.

Figure 3. The key technologies for 3-D parasitic extraction are a smart-cutting algorithm and a 3-D interconnect library with nearly 100 percent coverage.

The other way to extract each small section is to use a precharacterized library. Here, by thoroughly exploring the possible geometries that can result from partitioning, we build an interconnect library with each possible geometry as one entry. Figure 2 shows some typical libraries that can be encountered repeatedly throughout the extraction. By invoking fast field solvers for each entry, we come up with a closed-form formula best approximating that specific geometry or library. Then, during the extraction when one library pattern comes up, we just plug in some geometry parameters, such as widths and spacings, to get capacitance and resistance values.

These two approaches reflect the tradeoff between on-line run time and precharacterization time. Because the interconnect is built based on some knowledge, such as field distribution for each pattern and the generation of a closed-form formula, it can shift most of the on-line computation to precharacterization. Because designers typically only care about the actual on-line extraction time, the interconnect library approach is preferred. With the help of fast field solvers, the typical precharacterization can take one day, using multiple workstations.

A 3-D parasitic-extraction flow Figure 3 shows a typical 3-D parasitic-extraction flow. The complete system is composed of two main models and five submodules. The main modules are the utility for generating 3-D interconnect libraries and a selective net extractor such as Ultima-PE from Ultima Interconnect Technology Inc. (Sunnyvale, CA).

The submodules of the selective net extractor are:

• A 3-D field solver.

• An application programming interface for retrieving and sending data from the 3-D net extractor to a 2-D extractor.

• A smart-cutting module for breaking the net into smaller 3-D patterns.

• A library lookup module for matching 3-D patterns with the library.

• A net-merging and RC-netlisting module.

The selective net extractor is based on a 3-D field solver, the interconnect library, and smart-cutting technology. The interconnect library is automatically generated using the 3-D field solver with given technology information. The extractor breaks each net into smaller segments using smart cutting. For each segment, a pattern match is performed against the interconnect library. Each library pattern is parameterized in terms of width and spacing. This results in high library coverage--nearly 100 percent of the net segments are in the library. For these net segments, parasitic values are obtained using a closed-form formula with the geometric parameters. For the remaining net segments, a fast 3-D field solver is used directly. Finally, RC data for all the individual net segments are merged, and the full RC network will be output either as a Spice, a detailed standard parasitic format (DSPF), or a standard parasitic exchange format (SPEF) netlist or sent back to the 2-D extractor.

Conclusion For today's deep submicron designs, 3-D parasitic extraction is required. Three-dimensional extraction must be applied intelligently, because it is prohibitively expensive if it is used for all nets in a design. Indeed, it is not required for all nets, because most can be extracted accurately using 2-D methods. However, for certain nets (global nets or nets on the critical path), the additional accuracy that 3-D extraction provides can mean catching a design problem prior to tape-out, saving costly design and mask iterations and lost time to market.

Wayne Dai is an associate professor in computer engineering at the University of California at Santa Cruz.

Weikai Sun is the manager of parasitic extraction at Ultima Interconnect Technology Inc. (Sunnyvale, CA).

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integrated system design  January 1997