Logic Signals Need New Standards The problems with high speed won't go away. by R.T. "Tets" Maniwa

The TTL standard for digital-logic signal transfer seems to have outlived its usefulness. It was an excellent defacto standard when clock speeds were below 5 MHz and single function DIP packages contained the bulk of the circuitry. Now, however, the systems are running at over 100 MHz in system-on-a-chip ICs. The large ICs will have more than 400 pins, with over a hundred pins switching at any time.

Richard Crisp, of Rambus Technology Inc. (Mountain View, CA), notes that signal technology is the hardest problem to solve. In the past, everything used the first standard for all applications--TTL--the logic-level signaling standard, still in use today. Standards committees are struggling to apply bandages to the existing schemes. The signaling technologies necessary to transfer large quantities of data are not compatible with the older TTL standards.

Signal characteristics The main problems in the TTL standards are associated with the underlying physics. The thresholds for TTL signals are 0.4 V and 2.4 V, with CMOS outputs capable of full rail-to-rail swings. The progressions in the IC capabilities--finer lines, smaller, faster devices, higher density and complexity, higher edge speeds, and faster clocks--all contribute to more problems with the signals looking less and less like the classical timing diagrams or waveform displays. The voltage swing is a major contributor with measurable effects in power consumption, timing, and noise--both generation and susceptibility. Some of these effects are now being labeled as deep submicron effects, even though they have been around for many years. The signal issues are even more important for the board-level effects but, fortunately, are more easily controlled at the board level than on-chip.

Power consumption For the sake of argument, let us assume the typical output of any device faces a load of at least 25 pF and the system operates at a bus speed of 100 MHz. When this is expanded to a wide bus of 64 bits or more, the power figures become unmanageable. The power is calculated as ƒ(V ² ) for fixed F and C, where F is the operating frequency and C is the capacitive load ( P = F*C*V ² ). A 5-V signal will consume 62.5 mW for each 25 pF load toggling at 100 MHz. In comparison, a 3-V signal will only use 22.5 mW. The lower the voltage swing, the smaller the power to drive the capacitive load.

The PCB loading also contributes to rises in the peak power. The peak current required to charge a capacitor is represented as the load capacitance times the derivative of the voltage with respect to time. For example, the current required to charge a normal load is (I=CdV/dT), where c = 25 pF, V=4.0V and t = 1nS, resulting in peak current of I _peak = 100 mA per load. If we consider 32 lines changing at any time, the total peak current is 3.2 A. This current generates supply and ground noise as well as reduced noise immunity. The reduced noise immunity is a result of the supply voltage sag or "ground bounce" due to the voltage drops across the trace resistances.

Signal integrity Another problem with CMOS running TTL signals is the range of impedences. A CMOS input is a very high impedance, usually greater than 1 M(omega). At the same time, an output low is a very low impedance (0.2V/10mA= 20(omega).), while an output high is an intermediate level (0.2 V/0.1 mA=2 k(omega)). The CMOS output devices work in voltage mode near the linear range of the operating curve.

Signals are degraded by reflections and attenuation because the signaling impedance of the CMOS devices doesn't match the board impedance. Input acceptance is a term for how much of a signal gets to a receiver. It is expressed as a=Zo/(Zs+Zo), where Zo is the transmission line impedance and Zs is the source impedance of the driver.

Table 1
Interface standards
Logic Family		Description	Termination	Reference supply	Power supply voltage	VOH min	VOL max
BTL	Backplane Transceiver Logic	Low capacitance outputs, differential inputs	33 (omega)	2.1 V	5,3.3	2.1	1
CTT	Center Tapped Termination	A standard implemented in SSTL	10-100 (omega)	VCC/2	5,3.3	2.7	2.3
GTL	Gunning Transceiver Logic	Low capacitance outputs, differential inputs	50 (omega) to 1.2 V	0.8 V	5,3.3,2.5	1.2	0.4
HSTL	High Speed Transceiver Logic	Thresholds±200mv, CMOS outputs	50-70 (omega)	1.5 V	5,3.3	1.7	1.3
PECL	Pseudo ECL	ECL levels translated to+5 V	10-100 (omega)	none	5	0	0.9
RSL	Rambus Serial Logic	500 MHz serial bus	15-50 (omega)	2.1 V	3.3	2.4	1.6
SSTL	Series Stub Terminated Logic	CMOS with internal series termination	25-50 (omega)	VDD/2	5,3.3	2.7	2.3A
TTL	Transistor Transistor Logic	Totem pole or open collector outputs	none	none	5	2.4	0.55
STTL	Schottky TTL	Internal schottky clamped TTL	none	none	5	2.5	0.4
CMOS	CMOS TTL	Totem pole or open-drain outputs	none	none	5, 3.3	3.8	0.44
ECL	Emitter Coupled Logic	Bipolar current drive	10-200 (omega)	none	-5.2	-1.8	-0.9
CML	Current Mode Logic	ECL without the emitter follower	25-200 (omega)	none	-5.2	-1.1	-0.2

Since board traces have characteristic impedance between 10 and 200 (omega), the coefficient of reflection is almost always 1, so all the signal is reflected: (* = (Z _r -Z _o )/ (Z _r +Z _o )), where * is the coefficient of reflection, Z _r is the terminating resistance, and Z _o is the line characteristic impedance. When the signals reflect, they create noise and either constructively or destructively interfere. If the interference is destructive, the signal rise and fall times will be degraded, increasing the likelihood of glitches and timing problems. The reflections also cause the input stage of the following section to be in the linear part of the operating curve for a time equal to twice the signal transit time, greatly increasing power dissipation and creating the potential for device damage.

The issue of internal and external interface standards has been addressed in a number of conferences. At DAC '95, several papers addressed the techniques to alleviate the problems. The solutions for high-speed signals ranged from classical line termination techniques to specialized hardware to different signaling standards. The changes in devices and signaling standards are driven by a number of other issues in addition to the power and impedance problems mentioned above. One is the change from 5 V supplies to lower voltages; another is the need to operate at higher speeds.

Last February, the International Solid-State Circuits Conference (ISSCC) in San Francisco addressed the problem of processor to memory signaling. Because the TTL interface is a standard that has performed well for the past 30 years, it is automatically considered as the interface of choice. Now with system clocks exceeding 100 MHz and signal transitions in the fractions of a nanosecond, the engineering community has to seriously consider the alternatives. Some of the other transfer standards require more design effort--reference and termination supplies, line terminations, and other techniques for high-speed signals--but are much more likely to achieve the performance and signal integrity necessary for the next generation of logic systems. The families of devices included HSTL, SSTL, CTT, GTL, RSL, and LVTTL. Table 1 describes the standards and their operating characteristics.

The problems of signal integrity are exacerbated by the requirements for high through-put. Limits of expandability is a large concern as buses grow beyond 32 bits. The doubling of throughput by doubling the bus width is no longer a viable solution. The number of lines to control the bus interface and the bus itself become too large for any reasonable signal control scheme. The need for signal impedance control requires lines to be terminated at both ends of the bus, so the number of terminations will be twice the number of pins required to handle the bus.

One final issue for different choices in logic signaling will be the ability to use the interface for logic design. It makes little sense to receive signals in one format, translate them to a different format for internal logic functions, and translate them back to the external format when every nanosecond is critical and the translations could take up to a nanosecond each.

Future logic families will change the internal and external logic from the current CMOS levels to some other logic. The ideal logic family will use a small signal swing between logic levels. TTL levels should be restricted only to those low-speed signals that must interface to other parts of the system, like the parallel I/O ports. A separate packaged part for TTL signals, possibly optically isolated to minimize noise and power supply problems, could handle the signal conversion without affecting system or I/O timing.

Tets Maniwa is a technical editor for Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to: michael@asic.com.

integrated system design  February 1997