Modeling Devices for Performance Leading-edge designs require high-accuracy models. by R.T. "Tets" Maniwa

As integrated circuits progress down the path forecast by Moore's law, the need for better models has become imperative. The higher-performance parts need more accurate and robust models that scale to different processes to make the simulations and devices match as closely as possible. The highest possible operating frequencies make non-linear effects, increased contribution of parasitics, and more important second-order effects significant contributors to the overall performance.

HDLs manage the simulations of the function and performance of a circuit well at the logic level of abstraction. Even though the HDLs handle basic timing and delays, many companies use a device-level simulator such as Spice for very detailed evaluation of critical paths. Whenever performance is very close to the resolution limits of an event-driven simulator, a common reaction is to "do a Spice run." The mixed-signal and analog designs require the detail of the device-level simulations to achieve their design goals.

While increased accuracy is needed, designers also need fast simulation times. The higher-complexity models require more data per device and may include embedded equations. In addition, their increasing density and complexity imply more types of functions on a chip, including analog and mixed-signal circuitry. This increased design complexity adds to size and accuracy requirements, with the unfortunate result being that simulation times increase. The existence of multiple models based on simplifications and curve fitting exacerbates the problems by generating many invalid or conflicting solutions in simulators.

A growing problem is the proliferation of model types in the vendor community. Currently, models are generated to fit as many device parameters as possible. However, the curve fitting may be responsible for another Tower of Babel. The parameters from a model type do not translate directly into other models, and the underlying curve fitting means that even some of the same parameters do not match across models. Nevertheless, companies want to take a Spice listing of a critical circuit path from an existing circuit and use the simulation to evaluate the fab performance. They apply a fab's Spice models to the circuit to determine how well the fab process can perform on a known circuit. Therefore, the models are used as both a screen and a qualification procedure for a wafer fab based on the simulated performance of a known circuit. If the foundry does not support the same models, the designer has to convert the design and Spice netlist to the target process and re-simulate the circuit. This task can take almost as long as the initial design, especially when the models are completely incompatible.

The ability to extract parameters and model device behavior is crucial to the performance of the next generation of ICs. Some of the models in contention for primacy are MOS9 from Philips (Einhoven, Netherlands) and BSIM3V3 from UC Berkeley. Both of these device models use robust, open equations underlying their internal parameters. Some work on the model definitions has been shared by the developers of MOS9 and BSIM 3.x, so the two models are in fairly strong agreement. Sematech Inc. (Austin, TX) has developed a device-model test suite to compare models against the fabricated device performance. The model configuration control for BSIM3V3 will be through Sematech. Thus, the various parameters and their underlying equations will become stable and standard for the entire industry.

Table 1. The relative performance of the BSIM3V3 and MOS9 models in the Sematech test suite.

The previous generation of models for MOS devices included BSIM1, BSIM2, and proprietary models from the silicon vendors that all have various deficiencies with respect to actual device performance and robust simulation. The lack of consistency and correlation between the various models has created confusion and a high level of discomfort for designers who have had to wait for silicon to confirm the design performance. The pressures of time-to-market now preclude a silicon turn, so designers need their device models to accurately project the physical reality rather than an empirical curve fitting for sample devices.

The Fabless Semiconductor Association had a meeting in February 1996 to discuss the model issues. Martin Manley, of VLSI Technology Inc. (San Jose, CA), talked about the implications of Moore's law and said the SIA projections for device density in the next 15 years will drive a number of other trends. Smaller devices will enable higher logic densities but will also drive the supply voltages lower. The lower supplies create an incentive to reduce the threshold voltages V _t , with an unintended consequence being that devices on average will spend more time in the transition region between weak and strong inversion. The technology trends will make more of the small-device effects, such as "reverse short channel" and LDD modulation.

Zhihong Liu, of Berkeley Technology Associates Inc. (Santa Clara, CA), described the need for parameter extraction across all available device corners to ensure realistic data to input to the models. Some of the problems associated with many bins for model extraction are the size of the database as well as the lack of accurate and continuous binning while still not knowing if you have sufficient or correct bins. In many models, behavior within a bin is hard to predict because they are based on curve fitting.

Akis Doganis, of Mentor Graphics Corp. (San Jose, CA), used the Sematech benchmark suite to compare the BSIM3V3 and MOS9 models with the results shown in Table 1. One result of his study is the apparent need to develop statistical models for devices and interconnect to design for manufacturability. These data are not brought out in the device models, so the IC performance can be greatly affected by a parameter that is not easily simulated.

Bill Scott, former director of modeling software for Meta Software Inc., said that one paramount issue is the quality of models. MOS transistors have characteristics that have been modeled by fitting curves to the current responses for digital circuits, and to the conductance (Gm, Gds) for the analog circuits. The better models are BSIM3, MOS9, and Meta's level 28. The latest models have some physical basis in addition to some fudge factors to get a better fit to the physical devices. BSIM3 has gone through a number of iterations in its development. It is a public domain model from UC Berkeley (plus inputs from Cadence and others). The latest version of BSIM3V3 was released in October of 1995. The developers at Berkeley were conscious of industry issues and made significant changes in the models to rework the equations to have physical meaning and accuracy.

BSIM3V3 and MOS9 are new standards using open models (meaning the models are in the public domain). The developers shared insights and underlying technologies to come out with closely compatible and very similar performance. Now it is viewed as a political battle. The rival standards are vying for dominance. MOS9 is gaining wide acceptance in Europe, while BSIM3V3 is making its mark in the U.S. and Asia.

Benefits The move to common models will improve fab portability and enable designs that take full account of the inherent performance in the fine-line processes. A robust, accurate model will enable designs to be portable between compatible fabs, and it will also allow them to reuse existing design blocks. Common models ameliorate the difficulty of confirming fab migration by eliminating the model conversion or design conversion from one set of fab models to another.

In other areas, common fab models permit design and yield analysis and process-modification evaluation by providing a framework for the varying parameters. Scalable models allow easier device-parameter extraction for a process, since all physical changes in geometries are reflected in automatic parameter changes.

Tets Maniwa is a technical editor for Integrated System Design.

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integrated system design  May 1997