ASIC Issues

DSM Increases the Need for Experienced Design Teams Changes in technology will require different design styles for successful high-density ICs. by R.T. "Tets" Maniwa

The advent of deep-submicron (DSM) process technologies has created many new challenges for designers of the next-generation ICs. Multimillion-gate devices--with the capability of including large amounts of RAM and complex functions--are available now from a number of ASIC vendors. While the capabilities exist in the silicon, the design complexity of a million gates calls for (what may be) mutually exclusive requirements. On one hand, the designer needs to work at a higher level of abstraction to handle the design complexity and meet time-to-market schedules. The logic designer has enough problems just getting the logic and (static) timing correct. On the other hand, the design requires much more detail and analysis to ensure that the design meets the electrical, functional, and timing specifications.

These designs will require more than just changes in tools and design flows. Incorporating changes in methodology for deep submicron will drive the need for experienced teams and experts in many areas, because many of the areas that require special expertise aren't part of the designers' domain expertise. The time-to-market pressures and product lifetimes of less than a year have led many companies to create multiple design teams. This proliferation of design groups exacerbates the shortage of electronics engineers while simultaneously diluting the knowledge base in each team.

After the logic design is completed, it goes to the verification people, who now outnumber the designers in many companies. The philosophy for separate design and verification groups is to have the people verifying a design be "clean" in not having prior knowledge of the design. This presupposes that the verification team will not try to skip any verification steps as a result of a priori circuit knowledge. The problem is that the verification part of the team must understand the designers' intent as well as their code.

After verification at the RT level, the design goes to synthesis, that is, to a person who knows the details of the synthesis process. The synthesis engineer not only checks the RTL for syntax, but also tries to understand the design style for better optimization. A high-speed datapath requires different pragmas and constraints than some control logic or a state machine.

After the synthesis and verification of the gate-level netlist, the design goes to physical design. Now that interconnect delay dominates the total delay, the success of a design depends on a timing-driven design and layout regimen. However, the interaction of physical and electrical design causes a paradox. An accurate timing-driven layout requires that the design be complete (including layout-derived parasitics), but the final layout interconnect values necessary for accurate delay analysis don't exist until the layout is complete. The design needs a complete and accurate circuit topology to produce interconnect parasitics for analysis, but the transistor-level netlist isn't designed with any topology information.

The number of iterations for timing convergence is reduced when the designer provides an RTL floorplan with the netlist and works with the CAD group to anticipate layout-related issues before parasitic extraction. In addition to the floorplan, the design team now requires experience and expertise in parameter extraction. Not only is timng critical, but the nanometer processes with a submicron pitch for the metal need accurate interconnect information for signal integrity analysis. Parameter extraction is a function of the layout, and therefore a part of the CAD group, and also a part of the extraction and modeling group.

The wiring and interconnection problems are just a few of the plethora of issues that must be addressed for nanometer designs. In addition to expertise in parameter extraction and signal integrity, the design group needs expertise in the interactions between synthesis and layout, to keep the design from becoming chaotic--when a change in one area affects an unrelated area. Understanding which design parameters to adjust to make back-annotated netlists meet timing requirements will help reduce iterations and improve convergence to the specifications.

The active and passive devices need more and better characterization and modeling. The designers need to have accurate models of the devices at all levels of abstraction. In addition, the modeling group must map process parameters to electrical characteristics, especially for those processes in development. In addition, the modeling group monitors the performance of the fab and checks for process drift that could lead to reduced yields. These data on devices and models are also essential for process and fab migration. The areas of expertise for this set of functions are in device and semiconductor physics, not circuit design, so the knowledge base tends to be outside the normal range of most designers. At the same time, the modeling experts need to have some appreciation of design to ensure that the designs will map to the process.

Along with characterization and modeling, library development and maintenance are becoming more important. Even if the libraries are purchased from a third party, someone needs to constantly update and validate the libraries. At the primitive logic level, the design team must generate the multiple drive strengths for each logic element if they don't already exist. The libraries need good device models and characterization to accurately predict the analog behavior of the very high speed signals.

While all the design processes are proceeding, the other engineering disciplines are starting their work. The packaging engineers not only develop the packages, but also review the electrical, physical, and thermal characteristics of packages. In addition, they review the manufacturability of the packaged part by analyzing the physical structures and the die-package interfaces to determine if the manufacturing process will cause yield losses. The physical properties of the packaging materials, like flow and stress, will affect the yield, because packages are more than just plastic squirted around the die and lead frame.

Mechanical and printed circuit board engineers will review the manufacturability of the packaged part on boards--the physical attributes that influence overall system yield. They also check the design for important physical and mechanical features like board spacing and structural integrity. An example of one type of physical analysis is the placement of an IC with an integral heat sink. This part needs minimum air flow and spacing to the next-closest components to achieve proper heat transfer, but an airflow analysis is not sufficient if thermal analysis also indicates local hot spots due to power and activity in the air path. The system requirements for thermal stability may exceed the specifications if average and peak power for each subunit in the system is at its maximum.

Manufacturing engineers look at the effect of packages on costs and manufacturability as well as the actual flow for manufacturing. The IC with a heat sink will require special handling and sequencing to ensure that the package will fit into the handling equipment and that the package size won't interfere with any other component placement. In conjunction with the mechanical, PCB, and design engineers, the manufacturing engineers will review the system specifications to ensure cost-effective and reliable sources of supply while working with the purchasing and materials groups to develop proper order quantities and ordering lead times to secure complete kits of components for manufacturing.

In addition to the physical aspects of the manufacturing process, testing is consuming a greater portion of resources for all designs. Testing increases at some exponential rate of the growth of the gate count. The design and process complexity requires more comprehensive testing to capture design and manufacturing faults but can't increase the testing time to unacceptable values. Within the constraints of minimal test time and maximum test coverage, the test engineer needs to be as capable in design analysis as the verification group and also needs to know how to apply the most appropriate test strategy to the IC.

The many facets of the design process illustrate the need for timing-driven design, floorplanning, and placement using a concept of correct by design. The next generation of ICs will depend on the knowledge and interaction of a large body of experts to meet all of the specifications.

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integrated system design  October 1997