ASIC Technology

Low-Power ASIC Design

Here are some tricks and techniques to help you reduce power in an ASIC.

by Jerry Frenkil

ASIC designers today are faced with a common dilemma. On the one hand, product specifications dictate their designs must consume minimum amounts of power to meet cost, reliability, and energy efficiency goals. On the other hand, functional specifications imply that the ASICs must integrate more circuitry and run faster than ever to implement the desired functionality, which in turn drives up overall power consumption.

In the good old days of IC design, before power became a significant design constraint, most chips were designed without concern for their resulting power consumption. Lately, this approach has produced more than a few surprises, including schedule slips due to redesigns as well as cost overruns due to ceramic packages and heat sinks. Today, designers have begun to adopt, out of necessity, design methodologies and techniques that reduce power consumption.

Static and dynamic power An ASIC's total power consumption is composed of two different types: "static" and "dynamic." The primary distinguishing factor between the two is that dynamic power is frequency dependent, while static is not. Static power is defined as the product of the power supply voltage and a static current, which itself has two components. These components are "leakage current" and "through current." Leakage currents, which occur in all MOS devices, are the result of sub-threshold transistor operation and reverse bias diode leakage. Through currents also occur in normal operation but are caused by transistors being continuously operated in their saturation (always on) regions. They arise out of design decisions to employ analog techniques or resistive pullups. The magnitude of through currents is usually in the microamp to milliamp range. By comparison, leakage currents are parasitic effects and are usually of smaller magnitude and usually ignored.

Dynamic power also has dual components, "cell power," and "capacitive load power." Cell power is the power consumed internally by library cell primitives, such as nand gates and flip-flops. This component accounts for the power required to charge and discharge the capacitances internal to the cell as well as the crowbar currents that flow when the transistor stacks switch states. Capacitive load power represents the currents required to charge the external (to the cell) loads driven by each cell. Thus, the equation for dynamic power for an entire chip is given by--

where

and

The total power dissipation of an ASIC is then simply--

These equations, when computed over a number of clock cycles, produce time-averaged power that is used to analyze the effect of power on battery life, junction temperature, and package selection. Performing this type of analysis on a cycle by cycle basis can also produce a value for peak power, which is most useful in checking noise limits and determining the number of power and ground pins needed to minimize ground-bounce effects.

Figure 1a & 1b. Figure 1a shows a flip-flop with recirculating data, while Figure 1b shows a flip-flop with a gated clock.

An effective low-power design process involves not just design techniques, but an overall methodology, as well. The methodology consists of thinking about power at all levels of design. It utilizes tools and techniques at each of the levels. For example, early specification and analysis can help with critical architecture decisions in the power domain. The same is true in the performance domain. Tools that enable early analysis are essential, as are tools that can work at the various design abstractions such as RTL, gate, and switch. While tools are not the entire answer, they are a critical component. They enable the designer to make informed decisions as to which architecture or design technique is most power efficient. This is where the battle is won or lost.

Design techniques A variety of design techniques, at several different levels of design abstraction, exist for minimizing power. These abstraction levels can be described as Technology, Circuit, Logic, Architecture, and System. To minimize power consumption to the greatest extent, decisions made at each level of design abstraction must account for power.

Referring back to the equations for total power, it is evident that power can be reduced by lowering the voltage, capacitance, signal frequencies, or cell energies. Specific techniques will address one or more of these factors at a particular level.

Capacitance and cell energy reduction The best example of capacitance reduction is the use of a multiplexed bus, as opposed to a tri-state bus. Consider a bus with four drivers and one receiver. Implemented as a tri-state bus, the power consumed in driving the bus is proportional to the total load capacitance on the bus. Most of this is due to the self-loading of the tri-state buffer outputs. Implementing the same function with a four-to-one mux in a 0.6-µm, 3V, standard cell library produces a savings of about 13 percent. This improvement is due to the fact that the four-to-one mux does not have to drive the output capacitances of the other drivers, as seen in the tri-state bus. A further improvement results from preventing the possibility of bus contention, which is always a concern when using tri-state busses.

Energy = the amount of charge moved
through a voltage
= Q * V
= (C * V) * V
= C * V
2

Power = Energy per second
= E / t
= (Q * V) / t
= (Q / t) * V
= I * V this is the familiar equation
for static, or DC, power
A different derivation yields dynamic power.
Power = E / t
= (Q * V) / t& where Q = C * V
= (C * V * V) / t
= C * V
2
 * f where f = 1 / t

Definitions:
Q = charge
[coulombs]
C = capacitance [farads]
V = voltage [volts]
I = current [amps = coulombs per second]
E = energy [joules]
P = power [watts = joules per second]
t = time [seconds]
f = frequency [hertz = cycles per second]

Reduction of cell energy is usually a relatively simple case of choosing particular libraries or cells that are the lowest power alternatives. An example would be the use of an output buffer with the minimum drive strength and power required to meet timing. Another example would be the choice of a particular cell library over another. It is interesting to note that standard cell libraries often are more power-efficient than similar gate-array libraries, due to the use of varying transistor sizes and optimized layouts.

Yet another example of cell energy reduction is the use of flip-flops without local clock buffering. Most ASIC flip-flops utilize local clock buffering where a single-phase input clock is buffered and inverted to produce a true and complement clock internally. Thus, when the input clock switches, the local buffers switch whether or not the flip-flop's output changes state. This can result in a significant amount of wasted energy.

Figure 2a & 2b. The simple decoder in Figure 2a continuously activates downstream logic, while the decoder with enable in Figure 2b only changes state when enabled.

Frequency reduction A key concept in low-power design is the minimization of energy waste caused by operations and signal transitions that accomplish no useful work. In this light, frequency reduction is not necessarily the global reduction of clock frequency, but rather the reduction of signal frequencies on a localized basis. Perhaps the best example of this is the use of gated clocks.

Gated clocks are used to turn off the clock to a particular module when that module is inactive. This saves on clock power, as the local clock line is not toggling all the time. Consider the case of a data bus input register. With conventional clocking, as shown in Figure 1a, the register is clocked all the time, whether new data is to be clocked into the register or not. If the register must hold the old state, the register's output is fed back into the "D input" through a multiplexer whose select controls whether the register clocks in new data or recycles the existing data. With a gated clock, as seen in Figure 1b, the signal that would otherwise control the select line on the multiplexer now controls the gate. Consider the power savings for a multi-bit register, where the register is only clocked half as often. Clock gating here reduces the power consumed in driving the register's clock inputs by 50 percent.

The gated clock scheme also reduces the power consumed within each of the register's flip-flops. With a gated clock, the power consumed in each flip-flop's internal clock buffers is reduced because the register is only clocked when the output is likely to change. In the multi-bit register example above, gating the clock produces savings and internal flip-flop clock power which are in addition to and exceed the savings due to driving the clock-load capacitance less often. Note that while gated clocks clearly reduce the power consumption in local clock networks, they usually lead to increased difficulties in timing verification due to the added complexity of the control signal setup.

A variant on the gated clock theme can be seen in the ripple counter. Consider two designs for a 4-bit counter--a synchronous counter and a ripple counter. In the synchronous counter design, each of the four flip-flops is clocked directly by the system clock during each cycle. In the ripple counter design, each flip-flop (except for the LSB) is clocked by the output of the previous stage. Thus, it is clocked only when it needs to change state, and no clocks are "wasted." Energy is saved because the effective frequency of each flip-flop's clock input is dramatically reduced. This reduces power consumption because the clock input capacitance is switched less often. Furthermore, the biggest power savings stem from reducing the average switching frequency of the flip-flops' internal clock buffering. In this case, the total power consumed by the ripple counter is about two-thirds that of the equivalent synchronous counter (637 µW versus 973 µW, running at 50 MHz).

Figure 3a & 3b. A split memory reduces power per read. The gated clock design reduces power even more at a moderate increase in device complexity.

Another example of frequency reduction involves the decoder. A change on a single decoder input results in two output pins switching state. Thus, it is desirable to "block" the outputs from switching unnecessarily. This is accomplished by using an enable on a decoder, as shown in Figure 2.

Consider the case of an address decoder on a chip's input address bus. If multiple chips sit on the bus, the address decoder will decode all addresses that "fly by," whether its chip-select is active or not. The decoder is consuming power each time the address changes. The same is true of all the downstream logic that is fed by the decoder outputs. Using an additional input, such as chip_select, as an enable to the decoder then blocks the outputs from changing when the select line is inactive. This saves considerable amounts of power.

In a similar fashion, power can be saved in multipliers by registering its inputs, then clocking the registers only when the multipliers will be active. This reduces the number of times the multiplier unnecessarily multiplies. Given that multipliers often consume large amounts of power, these savings can be significant. Again, the key concept here is reducing energy waste by frequency reduction. If the multiplier's results will not be used, it is better to prevent the data from entering the multiplier rather than throwing away its output.

Memory design Another key concept in low-power design is focusing on those areas that consume the largest amounts of power--these same areas provide the greatest opportunities for power reduction. Clocks are usually one of the major contributors, as are memories.

Perhaps the first issue to consider is simply the power consumption characteristics of the available memories (see Table 1). Many ASIC memories consume static power when the sense-amps are enabled; hence, they are usually a poor choice for a low-power application. Compare the power characteristics of two RAMs from a commercially available, 0.6-µm, 5V, standard cell library.

Another technique for reducing memory power borrows from the timing designer's vast book of tricks. In some cases, designers use two smaller memories instead of one large one. An example of this is shown in Figure 3a, where a 256 by 32 RAM is split into two 128 by 32 RAMs. Consider the effect

on the energy consumed during read cycles. Using two smaller memories instead of a single larger one, the number of read cycles is reduced for each memory to half that of a single memory. But since two memories are used, the total number of read cycles is the same. This is valuable because the energy consumed for a single read cycle is significantly less for the smaller memory (1.1 nJ versus 1.6 nJ). Accessing the memory for reads and writes at a 20-ns cycle time produces a power consumption for the single memory system of 119 mW. The memory system in Figure 3a consumes 78 mW. Further reductions in power can be achieved at the expense of some added complexity, as shown in Figure 3b. This arrangement reduces the power to 74 mW by gating the clock to the address register.

A full-chip approach Low-power design is a new challenge for most IC designers today. Fortunately, tools and techniques are available to help. The bad news is that there is no magic wand that will magically transform an entire chip into a low-power equivalent. To minimize power, a full-chip, multi-level design and analysis methodology is required. This methodology must focus on early analysis and each of the major design components: clocks, datapath, control logic, memories, and I/O. The methodology must also facilitate easy experimentation so that design tradeoffs can be explored, as illustrated in the various memory designs above. This type of design space exploration is key for achieving truly power-efficient designs.

Jerry Frenkil is the vice president of Low-Power Design at Sente Inc. (Chelmsford, MA).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  March1997