ASIC Technology

Managing Power in a Million-Gate IC Design

Part of the solution to managing power is to address the power supply connections.

by Don Hanson & Teng-Sheng Moh

Managing power in a million-gate IC design presents a challenge that has several acceptable solutions. HAL Computer Systems addresses the problem by using solder-bump technology and several internally developed and commercially available analysis tools. After working through the process of power management and analysis, we're convinced it's an integral part of today's and tomorrow's large-chip designs.

Signal integrity issues arise as a result of limited wiring real estate. There are three key areas of concern regarding power-related signal integrity: voltage (IR drop), ground bounce, and poor reliability caused by electromigration. Any of these can wreak havoc in a large chip, but combined, they're deadly.

IR drop If the V _dd and ground network is too resistive, or if the current on the power and ground lines is too high, then IR drops will develop within these networks. Consequently, the voltage of the V _dd node falls and the voltage on the ground node rises, decreasing the supply voltage at the circuit. This voltage drop has an adverse effect on the noise immunity of those circuits. In extreme cases, the circuits may stop functioning correctly. When the spikes occur, the voltage collapse between V _dd and ground is even more pronounced. The problem is to design the V _dd and ground delivery networks with small IR drops, leaving enough voltage across the devices to keep them reliably functional.

Ground bounce At the same time the designer struggles to control the power distribution network's voltage drop, ground bounce--another effect of device interactions--causes device errors. There is a subtle difference between IR drop and rise and ground bounce: IR drops and rises occur in the chip's active circuits, whereas ground bounce occurs in the quiescent part of the circuit.

For a synchronous design, when the clock switches, many of the chip's circuits switch. It's not a uniform power draw; instead, it's centered around the active circuitry, which sometimes is as little as 35 percent of all the chip's circuitry. When the spikes occur, a shock wave of current goes into the ground plane. It is like throwing a big rock into a pond--the concentric wave spreads outward from the centers of the active circuits, disturbing the ground level of the gates it passes. Sometimes the ground level is elevated enough to cause false triggering on the quiescent logic gates.

One way to minimize ground bounce is to limit the slew rate of all the chip's internal gates. However, there is an adverse effect of increasing the commutating current, which, in turn, increases the chip's heat dissipation. In this situation, the designer must make a design tradeoff--he or she must find a balance between reducing the ground bounce peak height and increasing the total power dissipation.

Electromigration The other big issue is the effect on long-term reliability caused by electromigration. In normal signal wires inside huge chips, the current can go in either direction. The average current flow is near zero, so the atoms don't move much. However, in the power and ground supply structure, the average DC current is not zero, so the atoms' movement is unidirectional. Moreover, if the current gets high enough, one pulse will scatter the atoms and open the wire.

Figure 1. The PWRCHK flowchart for the design shows how the tools and files are related.

On a large chip that has multiple layers of metal, connections are made between the layers through a contact cut, or via. These are holes intentionally made in the insulator between layers that allow the upper layer's metal to "leak" through and touch the metal of the next layer. The contact area is small, resulting in a measurable resistance and a redistribution of current flow through it. Generally, in terms of design features, a contact can carry less current than a wire. Therefore, electromigration limits are reached first at contacts, rather than in the wires or at turns in the wires. Enlarging the current path through contacts, either by using larger contact cuts or by using more of them at connection points, can solve this problem.

Electromigration is temperature-sensitive. As the temperature rises, the thermal energy and electrical field combine to increase the metal mobility. This effect reduces the amount of current the wire can safely carry. To decide how wide to make the wires so that the chip will last several years, the designer must determine how hot the chip will get.

Power analysis To some extent, HAL's power analysis process was invented out of necessity. Very little software is available to analyze power distribution structures. And until now, large chips didn't exist, so the tools required to analyze their power distribution weren't available. Because HAL is not in the software development business, we would have preferred to purchase the tools we needed (see Figure 1). Unfortunately, none of the tools available on the market at that time met our requirements.

The analysis of power distribution is most important in a finished chip. But we also use it to analyze pieces of the chip, for macros or special big cells. The power network is extracted from the mask information to get an overall picture of the power distribution. Some tools have to extract it piecemeal, then put it back together, because of the chip's size. The process of assembly and disassembly, however, is a function that HAL's internally developed tools perform. A new tool, PGR Editor--from Silicon Valley Research--works well for full-chip extraction.

Our designers generate three maps to assist in the power analysis. First, we feed the chip layout's GDSII into CheckMate, from Mentor Graphics, and extract a resistor network picture from the layout of the power distribution networks (see Figure 2). Second, we model each cell in the library with an abstract map of how its power current is drawn. We use output from Silicon Valley Research's GARDS tool to tell us where all the cells are placed. Combining these cells, we build a map of power consumption for the chip. Third, we make the map of the solder bumps to determine where power is supplied. The result of these three pictures--the resistor mesh, the power supply, and the power consumption--is a mathematical matrix of many equations, which is conceptually straightforward but not trivial to solve. Our proprietary matrix solver tool provides information about the current flowing.

The power consumption maps are associated with library cells. A default mechanism creates an adequate map for most of the small, simple cells. Each one is rated by the amount of power it consumes. This power is distributed evenly to the devices in the cell. Because our extraction includes the connections to those devices, the resistor mesh accurately identifies locations on the chip where the power goes. We take the cell's total power from the library and distribute it uniformly over its points of load from the extraction.

Figure 2. CheckMate is used to extract a resistor mesh from the actual
layout patterns.

This procedure works for simple cells, but a big macrocell may have 10,000 points, and macrocells are not uniform. A large amount of ground current may flow in some places, while a large amount of V _dd current flows in other places. For the larger macros, we generate a map file where we specify how much power current flows in certain subareas within the cell. Conceptually, it's the same as a small cell, but the power is not distributed uniformly over the cell's points of load.

The big macrocells contain their own power distribution networks. To design a big cell, the designer must perform layout, prepare the power map, and then run both together through an analyzer. The analyzer will determine if the cell has a problem distributing its power inside. The designer must review the analysis and make a judgment. The map may need to reflect power consumption more accurately, or the designer may need to add wire to the cell. Although there may be 30 to 40 large macrocells in one design, we make a map and do a power check on each to ensure that every cell works well (in the designer's opinion). This procedure also provides a good power map representation of all the cells.

Error detection, which results in hundreds of flagged places, is the next step. We compute the current density in every wire to determine if it exceeds the limit. The program has a lookup table that identifies limits based on wire size. Wires or contacts with excessive current are flagged. IR drops and electromigration violations are accumulated and sorted to identify the worst problems first. However, using solder-bump technology, we rarely see IR drop violations.

Electromigration violations require interactive editing, which means going back into the power distribution structure to widen a wire or to add another wire nearby. There are many paths from a solder bump to the point of load, and the current follows the one with the lowest resistance--wires that are short with respect to their width. Because resistance is a function of both the wire's width and length, an electromigration violation can occur due to a narrow wire path that is short enough to be the low-resistance path. The designer must either widen the wire to handle the current or, in some cases, remove it so the power current will find a different path. Often, an electromigration violation occurs, not because a wire is too narrow to carry the current, but because of the lack of a good path to the true point of load. In these cases, the designer must add another wire in an appropriate place to carry the current (see Figure 3).

In fact, as we explored violations, we found that the analyzer misinterpreted some layout issues. For example, the extraction process had trouble merging clusters of contacts that we used to improve the electromigration tolerance when we joined two power wires. As we poured through the thousands of errors, we found huge classes of errors that represented analysis difficulties, not layout problems. We wrote programs that included a dictionary of false errors and acceptable waivers so we could pass the error report through the filter and remove the false errors.

Figure 3. To identify potential defect locations, the electromigration violations are superimposed on the layout.

After the initial filtering, we worked our way through a smaller set of errors. We determined why the analyzer was calling each flagged error a problem and whether each flagged error truly was a problem. We added those instances to our dictionary of waivers and tracked changes through each subsequent run.

Figure 4. The tool displays the ground voltage rise as a function of x-y locations for a portion of the CPU chip.

In addition, by correcting the analyzer or the modeler, we were able to remove a whole family of false errors. We corrected the extraction we obtained from CheckMate, the output from the analyzer, and the errors that were filtered. Going through this process, we recognized the repetitive parts and put together programs to filter those out. However, certain errors required human recognition and repair. In those instances, typically electromigration errors, we had to decide whether there was room in the maze of wires to add another power connection or if we should put the error in as a waiver. The waiver mechanism had expanded to the point where we could put in overrides at specific locations, so that the program would just filter the error out.

It took about a day to run through the analysis programs, filter out the waivers, and make minor adjustments. It took another day or two for the designers to review the material and make additional changes. At the same time, other groups were tweaking the layout. The power analysis took place between wafer turns as the chip was finalized, so it didn't delay the chip's completion.

When we first designed our analysis system, the idea was to locate all violations, filter that information back to the program that generates the power structure, and widen the wires. However, that's not the solution. The nonintuitive point of violation indicates problems, but so far we've only been able to train people to solve them. It's difficult to correct these violations automatically: Power analysis is an interactive process. We keep track of what we've tried--if something didn't work, we can try a different approach the next time. Each set of changes requires running the analysis programs in an iterative process.

For HAL, a crucial piece of the power analysis is associated with wafer testing. Although we support solder-bump technology, the chips are still tested at the wafer level. This means that they must operate correctly, at a lower clock rate perhaps, with power supplied only through test probes at the chip's edges. Because wafer testing is used to decide which chips will be packaged, we must correctly assess whether the chip will work properly when packaged during this testing. An additional power analysis is performed with the power supply map changed to reflect only the probe pad positions (see Figure 4). This analysis is used to ensure that IR drops will not affect circuit functionality at the desired wafer-test clock rate. Because wafer test is not a prolonged operation of the chip under test, electromigration considerations are not a concern.

Using solder-bump technology is just one solution to key issues such as IR drop, ground bounce, and electromigration. An advanced router will also help to use precious silicon real estate appropriately for improved power integrity. The router should have the capability of editing and analyzing power nets on the fly. The success of the construction for the advanced router relies heavily on tight collaboration between the designers and the CAD vendors. *

Don Hanson is a senior member of the technical staff at HAL Computer Systems (Campbell, Calif.).

Teng-Sheng Moh is vice president of engineering at Silicon Valley Research Inc. (San Jose).

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integrated system design  September 1997