ASIC Technology

Designers Gain When IP Vendors and Pure-Play Foundries Team Up

Developing libraries and other IP in parallel with bringing a fabrication process on line gives designers the flexibility to choose the foundry and the IP that best meet their specific needs.

by David Fung and S.Y. Tan-Stahel

Although pure-play foundries have long been viewed as having a hands-off attitude about intellectual property (IP), today's quick design cycles demand a more proactive approach. To meet time-to-market goals, foundries must work with companies to have IP ready for designers to use before the need for it arises.

Just as traditional ASIC vendors are judged by the depth of their design support, pure-play foundries will be measured by the relationships they establish with IP and tool providers--in addition to their ability to fabricate high-quality silicon on schedule. To work effectively in this new environment, designers need to understand the relationships involved and how IP components fit into a customer-owned-tooling (COT) design flow.

IP comparisons Whether referred to as megacells or cores, IP components have emerged as a way to shorten time to market in the face of growing design complexity. The IP can range from processors to MPEG decoders to memory cells.

To tackle system-on-a-chip designs successfully, designers need an IP component portfolio available that contains everything from relatively simple cores, such as UARTs and Z80 blocks, to highly complex components. Simple components are fairly standard today and have little differentiation value. Even with the best implementation, they usually don't make much difference to the overall design.

In contrast, complex components help differentiate a chip from the competition. These components might include an advanced CISC processor, high-speed or low-power SRAMs, or an MPEG II core, each of which can serve as a critical part of a single-chip system. It is extremely important that these components be as fast and as small as possible yet consume little power. Thus the specifications for complex IP components will be a major factor when choosing a silicon supplier.

The type of IP components a designer chooses depends on the value assigned to different parts of the design process and on the flexibility required. Each judgment, in turn, depends largely on the component's functional and physical complexity. Functional complexity concerns the sophistication of the component's algorithm and architecture; physical complexity concerns the level of optimization of the silicon implementation as measured by performance, area, and power. Value increases with functional or physical complexity because of the difficult work required to achieve the complexity in state-of-the-art components.

A synthesizable RTL description of a leading-edge processor core would have enormous functional complexity but low physical complexity, for example. A fully routed processor core, on the other hand, is high in both functional and physical complexity. Process-optimized RAM generators have a medium functional complexity, but very high physical complexity.

Based on the levels of functional and physical complexity, the IP currently available falls into five categories (see Figure 1):

• Hard cores are cores that have been fully implemented down to the mask-level data required to fabricate the block in silicon. Typically, they are application-specific elements targeted at providing dedicated functions, such as an Ethernet interface or an MPEG decoder, and have very high functional and physical value.

• Physical components are memories, standard cells, and other blocks that are fully optimized for a specific semiconductor process. They are extremely high in physical value and low to moderately high in functional value and are a major factor in determining the performance and density of system-on-a-chip designs.

• Firm cores are soft cores that have been floorplanned (the basic design topology is established) or at least have some physical attributes and have been synthesized into one or more technologies to obtain performance, area, and power estimates. They tend to have higher functional value (floorplanning is needed for higher-complexity blocks), and their physical value is greater.
  
  

  Figure 1. The enormous quantity of IP blocks that is now available commercially can be characterized by the degree of functional value (the sophistication of the algorithm and architecture) and the degree of physical value (the extent of process-specific silicon implementation).

• Generic components are like physical IP components but typically use a common layout and electrical rules that allow portability across multiple processes. Because they aren't process-tuned, they are lower in physical value.

• Soft cores , the most common type of commercial IP components today, are a complete architectural and algorithmic specification specified in an RTL code description that can be read by a synthesizer. They can have any level of functional value, but because the design has no physical information and hasn't been tuned to a semiconductor process, their physical value is low.

Bringing an SRAM generator into play The need for a close partnership between foundry and IP supplier becomes apparent in the case of Artisan Components' four-transistor SRAM generator. Chartered Semiconductor had an advanced process available for fabricating four-transistor (4T) SRAM cells (in contrast to the typical six-transistor cells). A 4T cell requires the use of three polysilicon layers, one of which must be a high-resistance poly that allows each cell to have two pull-up resistors. The process must also provide extra interconnect capability and design rules that allow high memory capacity.

For designers to take advantage of the process, however, they had to generate their own 4T SRAM array for the process or buy this IP from a third party. Traditionally, few companies have had the expertise to generate the 4T layout in-house; often specialized memory vendors would handle such difficult designs and target them for a specific IC process.

In other words, Chartered had a valuable process available for anyone who wanted to use it, but many customers didn't have the ability to take full advantage of it. Chartered therefore went to work with Artisan Components to create an optimized 4T SRAM generator for Chartered's process.

In previous years, a typical pure-play foundry would have waited until a customer needed a 4T SRAM, then worked with an outside vendor to characterize the SRAM for the customer (see Figure 2). Neither the SRAM nor any other library component could be developed until after the fabrication process was developed and qualified, and the ASIC/ASSP design couldn't proceed until the library was ready. Companies risked losing valuable marketing opportunities between the time when a new process was qualified and when production began.

Ensuring that libraries and other IP are developed in parallel with bringing a fabrication process on line reduces the lag between process qualification and production. (At Chartered, the lag has been cut in most cases to less than a month.) The time compression is possible only by working proactively with IP suppliers, because IP development must begin long before the fabrication process is qualified.

Working together That type of close relationship between a pure-play foundry and IP suppliers provides an ASIC vendor model for designers. Such a model can offer the best fabrication services and IP. Designers can thus have the flexibility to choose the foundry and the IP that best meet their specific product and individual internal infrastructure requirements. This approach permits each company involved to achieve excellence in its core competency.

In the case of the SRAM generator, Chartered and Artisan Components worked together to develop a core cell design that is precisely tailored to Chartered's fabrication process. Artisan Components then developed the design views and other technology necessary to use the IP. A test chip containing a 1-Mbit 4T SRAM has been fabricated and proven functionally successful (see Figure 3).

The 4T SRAM cell for Chartered's 0.35-µm process measures 2.2 µm by 3.8 µm, compared with 5 µm by 7 µm for a typical 6T SRAM cell. Customers can therefore take advantage of a fourfold reduction in cell size, which translates into an enormous decrease in chip size and cost when designers use a significant block of SRAM. The planned migration to a 0.25-µm process will bring further size advantages.

Figure 2. If process-specific IP development and chip design follow sequentially, they can take two years (A). Overlapping process and IP development and EDA integration cuts the time by approximately 50 percent (B). Parallel development and integration speed the time by an order of magnitude (C).

Targeting the SRAM for different processes is simplified by the use of Artisan Components' Process-Perfect methodology, which follows a two-phase development. First, a foundation component is developed for a process generation; then, the component is tuned for a specific process. Most of the technology is usable from one process to the next. Typical Process-Perfect steps include redesigning the memory core cell and sense amplifiers and changing the layout to take advantage of the new process rules.

Implementing process-specific steps requires a great deal of interaction between the foundry and IP supplier. At various stages of the IP development process, the foundry may request that the IP supplier optimize area versus speed, power versus area, and so on. The IP supplier must work with the foundry's electrical rules (Spice models generally), as well as layout rules. It must analyze circuit designs based on the electrical rules and resize transistors or change transistor ratios, or both, accordingly. Contrary to popular belief, much of the value of the tailoring process lies in electrical tuning rather than sizing and shrinking circuits to fit the layout rules.

The IP supplier must also build and validate an example of the IP so that customers receive fully validated IP components. Circuit design and layout actually take less than half the time required for targeting IP for a specific process. Validation, extraction, characterization, and design view creation and modeling take the bulk of the time.

IP in the design flow How IP components are integrated into the design flow depends on the type of IP involved, but the primary consideration is the use of the various design views necessary to accomplish every step in the flow. A wide variety of views are required, since each tool often requires its own view. When providing a physical component or hard core, the IP supplier must provide all of the design views from initial concept capture through chip assembly. If the IP component doesn't change from one application to another, the supplier can create all of the views ahead of time.

However, a memory generator creates unique combinations of memory rows, columns, word size, and so on. Memory design views therefore can't be created ahead of time; they must be created dynamically when a specific memory instance is needed. Artisan Components' memory generator accomplishes this task through a graphical user interface (GUI).

To configure an SRAM, the designer begins by entering appropriate parameters that apply to all the design views. These parameters include the number of words and bits, operating frequency, ring width (for power and ground; this value is set to a default based on the other parameters), multiplexer width, drive strength, and access type (synchronous or asynchronous). The designer can also enter or change default parameters that are specific to each design view.

Figure 3. Chartered Semiconductor fabricated a 0.35-µm test chip for a 1-Mbit SRAM using Artisan Components' SRAM generator, along with two customer designs containing embedded SRAM.

If the designer is using Verilog or VHDL behavioral code for the chip's logic, the first SRAM view generated is the simulation model. After automatic generation using the GUI, the model is inserted in the design by instantiating it in the behavioral code, just like a library model. All IP blocks are instantiated at this time. The designer can then simulate the complete design at the behavioral level.

Since the SRAM generator provides a Design Compiler model on demand, the designer can synthesize the rest of the design into gate-level primitives and use the gate-level SRAM model provided. Gate-level timing analysis can now be performed. The SRAM generator can also provide a netlist for gate-level simulation and a Motive model for timing analysis.

Moving into layout, the SRAM is still an instance. If Cell3 is used, the routing abstract is loaded into the Opus library and the GDSII file is generated; if not, a DEF file is used.

After placement and routing, wire delays can be back-annotated to the timing analyzer. If designers find timing problems and determine that the aspect ratio of the SRAM is preventing optimum routing, the generator can produce the same RAM with a different aspect ratio. The GUI graphically shows how the aspect ratio changes as the designer varies the words, bits, and multiplexer parameters. Designers can also increase or decrease the output drive of the SRAM to do in-place timing optimization. When all simulation and timing analysis is complete, the SRAM generator streams out the GDSII file for use with the rest of the chip's GDSII description. Designers can also write an LVS netlist, including the SRAM LVS, to compare the GDSII layout against the target schematic.

The decisions involved in designing today's system-level chips reach into the fundamentals of intellectual property values. Designers can work with a traditional ASIC vendor and accept IP that the vendor makes available or choose a pure-play foundry that supports a wide range of third-party IP components. When using a pure-play foundry, designers can integrate high-performance IP from third parties, design the IP in-house, or use off-the-shelf chips alongside the primary ASIC. Each choice entails cost and performance tradeoffs.

Clearly, success lies in creating the highest-performance design in the shortest possible time, and doing that demands the use of the best IP components possible. A close working relationship between the foundry and IP supplier makes those components available to every designer in a timely way. *

David Fung is a product application manager at Artisan Components Inc. (San Jose).

S. Y. Tan-Stahel is a director at Chartered Semiconductor Manufacturing Inc. (San Jose).

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integrated system design  December 1997