System Design

Mixed-Signal Modeling for ICs

The challenges of analog and mixed-signal design call for different modeling and simulation technologies.

by Jim Holmes, Felicia James, and Ian Getreu

Top-down design techniques for full custom, digital ASICs are prevalent throughout the design community, but comparable capabilities for analog and mixed-signal blocks are less clear. Analog design inherently involves many more key parameters at any level of description, and these parameters can vary significantly not only across different analog or mixed-signal functions but also across different implementations of the same function. Determining a valid modeling and parameter extraction flow is difficult. At Texas Instruments (Dallas, TX), we have established general guidelines and decision points to make analog and mixed-signal modeling more practical.

When developing the modeling strategy, keep in mind the three major components of the design development process. First, top-down design refers to a design style that focuses on the system requirements first. Typically, the chip is described algorithmically to verify that its specifications meet the goals of the end-system. As the design becomes populated with actual circuits, it is necessary to verify that these circuits meet the requirements defined at the chip level. This second step is referred to as "design verification." Third, test development can occur throughout the design process since you can use the testbenches and the models for simulation to develop the test program.

Define the simulation plan The first step to building a viable modeling strategy is to clearly identify the simulation goals. There is no substitute for a well-conceived simulation plan. It starts with defining which performance characteristics can be represented algorithmically, functionally, or parametrically. Typically an algorithmic representation works best for "what-if" analysis during the system design phase and simulates the fastest. A functional model tends to be a useful tool for interconnect verification and a mix-and-match simulation strategy. In the case of mix-and-match simulation, certain high-level models will be replaced by lower-level blocks (possibly down to the gate or transistor level), while the rest of the system remains modeled at the high level.

Key parametric concerns for the design can drive decisions regarding the level of detail that is added to the models. Often a single block may be represented by several levels of models. An example is an analog to digital converter. The algorithmic model merely defines how an analog input is output as a digital value. The more complex implementation includes additional effects such as the role of the write, conversion start, and read pins. The functional representation describes the building blocks of the actual ADC topology. For instance, the model for a successive approximation ADC includes models of the SAR, input comparator, a latch, and other digital gates. Each of these blocks has both algorithmic and functional models as well. Since one of the desired outcomes of the modeling effort is to verify connectivity within the chip, it is critical that each model includes all pins that exist within the actual silicon implementation.

In addition to considering the modeling strategy, it is important to take the time to explicitly list each simulation that you will need for the project. Even though some simulations are dependent on the final implementation, you can anticipate most key chip-level simulations when the specification is available. Be sure to include the type of analysis required for each test--transient, noise, AC, and DC. Other factors include "real world" effects such as thermal and electro-mechanical analysis. The more the chip interacts with a non-electrical world, the greater the risk that pure electrical analysis does not adequately reflect the behavior of the chip in the final system. For example, a simple inductor is a poor model of a motor. Including a detailed motor model allows for the simulation of the effects introduced into the chip when a motor hits a stop.

Some items in the simulation plan will translate directly to the specification, while others are necessary to determine correct functionality. The simulation plan tends to be more complex than the actual chip-level specification (see Table 1).

To reiterate, PLAN FIRST. The time taken to write down the simulation plan and modeling strategy first can prevent wasted effort later. The simulation plan can be a living document and expand as the design materializes, but it will be an invaluable aid to the product development process.

Select the modeling strategy Now that the plan is complete, it is time to determine how to implement the models. Assuming that the final chip is mixed-signal with a reasonable amount of random logic, the simplest solution is to use Verilog or VHDL as the modeling language. Verilog does not allow real numbers as pins, so some tricks are necessary. It is possible to do a real-to-bits or bits-to-real conversion within the model to pass real numbers across block boundaries. Selecting a digital language maintains capability with standard digital top-down methodologies. Review the simulation plan and determine whether any of the simulation requirements preclude the use of a digital language.

If the digital language is insufficient, consider whether an analog or mixed-signal language or a generic high-level language, such as C, best meets the system requirements. Some of the high-level modeling tools available today for specific end-systems, such as communications, may be based on C or C++ models that can comprehend DSPs and their software. Other end-markets may be better served by an analog or mixed-signal modeling and simulation tool, such as the Saber simulator from Analogy Inc. (Beaverton, OR), with its MAST mixed-signal and mixed-technology HDL. These tools can comprehend difficult loads such as motors and other non-electrical effects. The final choice will allow a mix-and-match strategy between behavioral, functional gate, and transistor-level representations of the various blocks within the chip.

Listing 1 shows a segment of an operational amplifier behavioral model. This particular model uses the MAST modeling language. In this portion of the code, a transfer function and other mathematical equations represent key behaviors of the op amp. Even though you can break the op amp further into blocks--such as the input stage, gain stage, and output stage--you do not gain much additional value by subdividing it into another level of behavioral models. At this point, it is practical to choose between simulating the behavioral model or the full transistor-level implementation (see Figure 1).

Just as you characterize transistor models by comparing simulated data to measured data, you must also characterize behavioral models. In the case of top-down design, the model exists first. As the circuit design materializes, each block must be verified against its model. You should think of the model as the specification. Your simulation plan defines the initial characterization plan. Throughout the design, surprises will occur, and the simulation plan will be a living document that captures new conditions and criteria that may impact the performance of the chip. You will need to input some of these new behaviors back into the behavioral model to see the impact on the full system.

Figure 1. A section of the op amp transistor-level schematic. The transistor-level schematic shows some of the internal devices in a op amp.

Consider your modeling strategy carefully because once you start writing models, you will want to be able to reuse them. If you select a modeling strategy for one chip that does not extend to the next-generation version, you will waste a considerable investment in modeling. Due to the unavailability or immaturity of the current standards for analog and mixed-signal modeling languages, it is not possible to "plug and play" different models in the current EDA simulation environment. As the languages mature, portability across tools will become less of an issue.

Implementing the models For analog and mixed-signal circuits, a schematic remains one of the best mechanisms for managing the design. Because each block can be represented in multiple ways, it is critical to maintain correct hierarchy and interconnectivity. Multiple levels of hierarchy occur to a much greater extent in integrated circuit design than in PCB design. As a result, many of today's tools do not significantly help the design engineer manage the hierarchy. Establish a policy and owner at the beginning of each project. The owner will manage the pin list for each block. Every model should always include all valid pins for the block, even if the pins are not functional within that level of abstraction. An interesting conclusion to be drawn from this is that the chosen simulator must be able to accept a pin with only one connection.

At the beginning of the design, the pins for each block are not defined. As the design progresses, it is important to continue updating the models with the appropriate pins. This technique allows for the mix-and-match strategy to verify lower-level blocks and connectivity. Use the system-level testbench throughout the top-down design, design verification, and test development processes.

Figure 2 shows an op amp within a larger VCM block of a servo hard disk drive chip. Note that even for a simple operational amplifier, numerous pins connect this block within the chip. Validating this connectivity becomes crucial in the chip verification stage. A schematic versus layout verification tool can prove that the layout matches the schematic, but it cannot determine whether the connectivity behaves as intended by the designer.

One common mistake of initial attempts for top-down analog and mixed-signal modeling is to ignore many of the pins. Simplification makes the modeling task easier, but it can jeopardize the integrity of the final results. Consider adding signal polarity checks that can tell whether an enable should occur on high or low level, actual values of bias currents, or supply voltage, etc. Also check whether a specific voltage supply is driving the block, which is important when numerous supply voltages are available on the chip. Often one supply will be "quiet" while another is "noisy," so just verifying the magnitude of the voltage is insufficient.

If the modeling strategy results in the need for co-simulation, use extra care when modeling the interface across block boundaries when that boundary also serves as the simulator boundary. A single-kernel simulation solution minimizes the risk of introducing false problems that are due to data transfer between simulators. A more serious risk is that real problems will be missed because the interface model is not accurate. These problems typically result from inaccurate load or timing models across the boundary.

Figure 2. Placement of the op amp within the VCM block. The block-level schematic shows the interconnections of the op amp to other parts of the circuit.

Modeling and test development Having a top-down modeling strategy can impact the test-development process, as well. When a behavioral model of the chip is available, the test engineer has access to key information for test-program development. Tools are available in the marketplace today that enable the test engineer to simulate the chip with the test program. This capability allows the test engineer to begin debug long before initial silicon. Teradyne Inc. (Boston, MA), Analogy, and Texas Instruments are currently co-developing a product that supports the top-down methodology in use at Texas Instruments.

Not only does the full chip-model help the test engineer, but the simulation plan also forms a foundation for the test plan. Involving the test engineer earlier in the development process generates better communication between the design and test functions. Also, the test engineer can identify potential testability issues early in the development process, when design changes are easier and not costly. Much of the test-program development-time now occurs in parallel with the design process. This change in development methodology helps force design and test to stay more consistent with the test stimulus for both the simulation and the final test program. The end-result can be a reduction in the total time to market.

Conclusion Incorporating analog and mixed-signal blocks into a top-down design process is a challenging task. This type of flow requires a dramatic change in the approach to the design task. Our experience indicates that a serious commitment to making the change is mandatory. However, the results in terms of faster reuse, higher quality designs, and improved test-program development are really significant in time-to-market and product quality. Having a top-level simulation of the chip within the target system helps everyone involved in the project: the customer, marketing, and design and test engineers.

Jim Holmes is a member of Mixed-Signal Products EDA Team at Texas Instruments (Dallas, TX).

Felicia James manages the Mixed-Signal Products EDA Team at Texas Instruments (Dallas, TX).

Ian Getreu is the vice president of technology development at Analogy Inc. (Beaverton, OR).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  June 1997