System Design

Solutions for H/W S/W Co-Design

The increasing design complexity of a system on a chip requires software to be integrated into the design flow.

by Anne Hilow and Jim Morizio

In the highly competitive ASIC market, fast design turnaround, low cost, and high yield are critical factors for success. At the same time, increasing product complexity and shifting design requirements continue to create new challenges in design verification for both ASIC designers and their design tools. Designers now not only contend with quality issues, but must make tradeoffs between hardware and software implementations. Ideally, a verification that the hardware and the software work correctly together would occur during the design process. Until hardware/software co-design technology matures, designers will need first-pass silicon as early in the project as possible to verify that the software works with the hardware.

Meeting today's aggressive timetables Today's ASIC design teams face numerous challenges. Most prominent among them are shortening design cycles resulting from increasing time-to-market pressures. In addition to these pressures, software complexity has grown exponentially and the need to verify embedded software against working silicon has also increased. Most ASIC teams build extra time into their design schedule based on the assumption that the design will need to be respun due to undetected bugs or additional functionality the software cannot handle. Since the hardware verification portion of a design cycle ranges from 50 to 80 percent of the overall time spent on the design, a hardware designer may postpone certain functionality for the next revision simply due to lack of time in the schedule. In addition, faced with a tight schedule, many hardware managers opt to push a design through with a less-than-ideal set of functionality based on the assumption that they'll "fix it in the software."

With the increasing complexity of today's ASICs, design verification has become a critical component of assuring overall product quality and performance. Early in the design process, ASIC designers typically quantify design problems into manageable representations using models that lend specific insight into hypotheses being tested before hardware is actually built. The complexity of these ASIC designs typically disqualifies the use of one unified model to verify all aspects of the design. As the ASIC design matures, many different hypotheses are tested and many different models are used. To achieve acceptable performance and accuracy, each model is designed to work in conjunction with one specific verification tool. Multiple verification tools are required to ensure a complete design verification.

Currently, most ASIC design engineers use a methodology that runs these multiple simulators and verification tools separately--yielding information that is specific only to the submodel of the designs for which the individual simulators and verification tools have run. Large ASIC designs are already partitioned into multiple modules to make the design flow more manageable. The modules are "sewn" back together during floorplanning--a prelude to actually placing the ASIC cells onto silicon. The designers then get some initial timing information from placement to understanding how close they are to the targeted critical path requirements. Ideally, as many timing issues as possible need to be caught prior to floorplanning and the physical design stage, which is a time-consuming portion of the overall cycle.

The sheer complexity of 400-kgate to 100-Mgate designs has caused exponentially increasing design iteration cycles. Decreases in verification time through multi-kernel simulation or increased design verification performance is a benefit to the designer and critical to hitting time-to-market schedules. If verification time can be reduced, the ASIC designer has gained additional time to explore the design space--testing possibilities of moving more code to silicon, or moving certain functionality to software based on the results of early verification. If the ASIC designer has the time to complete these "what ifs" and still meet an aggressive schedule, then the overall quality and functionality of the ASIC can be thoroughly characterized, if not significantly improved.

Figure 1. The microcontroller has a mixture of analog and digital subsystems that complicates full chip verification.

One solution to these problems is co-verification--the real-time connection of two or more simulators or verification tools via a synchronization algorithm built into a co-simulation backplane. Using standard protocols that are technologically independent of any of the simulators that have been integrated into the simulation environment, co-simulation backplanes provide unified control and the flexibility to expand or change the simulation configuration without changing the design verification flow. For instance, in a design environment with only one simulator, a netlister is used to translate the design database into a model suitable for simulation. In a co-simulation backplane, the process is referred to as "design partitioning." Design partitioning differs from netlisting because it generates many netlists from a single design representation and automatically creates special communication elements that permit each simulator to converse in a standard protocol with the backplane or other simulators as "peers." This technology is critical to co-simulation because it would be impractical for a designer to generate the complex interconnections between simulators using a manual process.

With the increasing reuse of intellectual property (IP) in the design process, the accurate timing model translation between different formats becomes more problematic. Co-simulation is the only current technology to address this issue. In addition to partitioning technology, a co-simulation backplane establishes and manages the run-time control and communications that permit multiple simulators to run simultaneously. One of the critical aspects of real-time communications between design verification tools is synchronization--a technique used to dynamically control communications between simulators and design verification tools. By synchronizing efficiently, simulation backplanes can couple analog, digital, structural logic, behavioral simulators, hardware accelerators, and timing emulators into a unified "super-simulator."

To ensure accuracy while meeting time-to-market pressures in the real world, design teams now use these super simulators to compress the time it takes to get the operating system to silicon faster. This strategy ensures that hardware and software work together. The hardware is quickly turned around, enabling software designers to run it against working silicon. Working silicon may demonstrate behavior that is not modeled well--such as actual performance over temperature and voltage variations, or the effect of packaging on silicon performance--therefore silicon for system and software debugging is needed as early in the design cycle as possible.

While some advocates of hardware/software co-design believe that development of software on simulated hardware would achieve comparable accuracy, in real-world applications, the risk of delivering less-than-optimal silicon may have profound business implications. Today, the most reliable method of providing a good embedded software development is a rapid ASIC development program that guarantees first-pass silicon success. Currently, the tools do not exist to effectively run software on simulated hardware. As a result, designers must rely on methodologies such as co-verification to maintain quality while meeting aggressive deadlines. With co-verification, vendors have the freedom to develop more aggressive project schedules, potentially allowing for more projects to be developed in a given year. When combined with the ability to reuse IP, vendors have significantly strengthened their competitive position.

First-pass silicon success at Mitsubishi A good example of how these concepts have been applied to real-world design problems is at Mitsubishi Semiconductor of America (Raleigh Durham, NC). Recently, to meet a customer's deadline for software development on a new design, the design time for a complex 8-bit controller had to be slashed, and in-depth verification needed to be performed in order to meet the goal of first-silicon success. Previous experience had shown the importance of thorough simulation in finding design problems before going to silicon. Therefore, it was decided to simulate as much of the project as possible, including full chip verification with mixed-level simulation. This could be performed using Verilog-XL, from Cadence Design Systems Inc. (San Jose, CA), in Verilog-XL incorporating behavioral analog models, but low-level verification of the analog-to-digital interface would also be required. Existing design capabilities would have to be utilized as much as possible, with little or no time for adoption of new tools and retraining (see Figure 1).

The design team on the project consisted of 12 engineers that were supported by 3 layout designers. The project had a 12-month deadline in which to deliver working silicon. The microcontroller design required more than 400 kgates running at 10 MHz, to be manufactured in a .8-µm CMOS process. Fourteen macro-functions, including FLASH A/D converters and a phase locked loop (PLL) frequency synthesizer, surrounded an 8-bit processor core. Top-level design capture was performed with Design Architect from Mentor Graphic Corp. (Wilsonville, OR), digital macros were simulated with Verilog-XL, and analog components were simulated using Spice. However, the PLL, which provided a critical function for the chip, contained analog and digital components in the same feedback path. It required exhaustive simulation, but doing so in Verilog-XL was not accurate enough, and complete Spice simulations would take too long.

The existing design environment included tools for both digital and analog simulation, but no mixed-signal capability. The analog design process and the digital design process never met, so the only options for testing A/D interfaces or mixed-signal feedback loops were to wait for the test chip or run the design in Spice and wait two months for the results. Neither of these was an acceptable option.

The design team had been using PowerMill from Synopsys Inc. (Mountain View, CA) for transistor-level power analysis, achieving high accuracy with short run times. For the new project, the team needed to combine the speed and accuracy of PowerMill with the digital simulation capability of Verilog-XL so that the PLL could be thoroughly wrung out before committing to silicon. To leverage existing tools and environments, the design team turned to Precedence Inc.'s (Campbell, CA) SimMatrix software simulation backplane that integrates multiple simulators into a unified concurrent simulation solution. Synopsys ' Vertue, one of Precedence's co-verification partner's solutions, integrates TimeMill (PowerMill's core simulator) and Verilog-XL into a mixed-signal simulator through SimMatrix (see Figure 2).

Figure 2. The analog and digital simulators are able to interact with each other through the SimMatrix interface.

Within two weeks of installing Vertue, the PLL was simulated closed-loop to frequency lock, representing nine-tenths of a millisecond of real time, in just 79 hours, a comprehensive verification step that would be completely impractical with Spice. Other Vertue simulations showed more than an order of magnitude speed advantage over Spice and accuracy within 5 percent. Vertue was also used to verify the connectivity and timing of all A/D interfaces and for timing verification of the PLL interface to the processor core's data bus. Using Vertue saved months on the design cycle by isolating a design problem in the analog-to-digital interface that previously would not have been discovered until after manufacturing an expensive test wafer.

Co-simulation enabled the design team to meet the goal of first-silicon success by providing full chip verification with mixed-level simulation. Along the way, the design team uncovered a number of additional benefits to co-verification. The high degree of accuracy of the co-simulation verification process facilitated the reuse of the PLL in new designs without the need for complete low-level verification of the macro. This saved time and eliminated the potential problem of not discovering until test silicon an interface bug in future designs.

True hardware/software co-design At Mitsubishi, the design team anticipates that future projects will require even higher levels of interactivity within heterogeneous simulation environments--many analog and mixed-signal applications are now being wrapped around a core processor. As a result, the design team will continue to pursue creative ways to adjust the design process. Co-simulation has now become a permanent part of the design methodology at Mitsubishi since other options, such as hardware/software co-design, have yet to completely solve the problem of multi-kernel verification.

Multi-kernel verification reduces training time by allowing designers to use the interface they are most comfortable with for the design process. In addition, the reuse of third-party and legacy IP has become key to getting products to market quickly and to the introduction of products with capabilities acquired from other sources or newly merged businesses. Only multi-kernel verification offers the necessary interoperability to achieve a high degree of product quality while meeting rapid time-to-market schedules.

Any given design will demand an optimal verification environment. Current options for hardware/software co-design are only capable of running a single simulation or verification capability at a time. While in theory, hardware/software co-design would optimize the design process and reduce time-to-market, without the ability to verify a complex design, this methodology would increase the risk that significant bugs or design flaws would remain undetected until test silicon. Co-verification allows maximum flexibility and minimum time to manufacturing for companies faced with design modules from multiple sources and with designers restricted by aggressive delivery schedules. Ideally, the hardware/software co-design process will speed time to market while maintaining current quality standards. Until current standards can be met with hardware/software co-design process, co-verification will remain the preferred way for design teams to ensure quality standards can be met on tight delivery schedules.

Anne Hilow is the product marketing manager at Precedence Inc. (Campbell, CA).

Jim Morizio is a senior staff engineer for mixed-signal design at Mitsubishi Semiconductor of America (Raleigh Durham, NC).

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  July 1997