EDA Platform

What Really Happened at DAC This year's themes, though less obvious, portend fundamental changes for designers. by Steven E. Schulz

If you didn't make it to this year's Design Automation Conference, you missed a lot. No, I'm not referring to Scott McNealy's shameful and insecure keynote address, nor the "ghost of Gerry Hsu" love-in with Joe Costello at the CEO panel. I mean some hopefully significant trends. Having attended more DACs than I care to admit, I think this one carried more subtle, yet far-reaching, messages for designers.

I believe the main themes of DAC crystallized into four key areas:

• Design reuse, intellectual property, and core integration
• Synthesis wars
• Verification and verification support
• Deep-submicron effects

The first three address the growing system complexity problem; the fourth, the silicon complexity problem. The EDA vendors are clearly seeking more revenue growth by moving upward in the food chain, yet they seem less focused as a group on solving the big, ugly EDA technology issues that I expect will be a barrier to that growth. The semiconductor companies are quite worried about this trend, and we can expect an increase of internal tool solutions for companies whose competitive advantage requires staying on or near the leading edge.

Design reuse, intellectual property, and core integration For the first time at DAC, numerous providers of intellectual property (IP) were selling their wares (mostly "soft wares," or synthesizable RTL blocks). Also, a number of library conversion services are now available, mostly for resizing hard macros for process rule shrinks. Several ASIC suppliers announced rather comprehensive core programs, setting new benchmarks for credibility in this era of reuse. Yet the big news is that the EDA companies, who only last year mentioned a few plans, came out in force with press releases announcing their entry into the IP fray. Most notable was the Mentor- Synopsys agreement for certified flows of Inventra models through the synthesis-to-CBA foundries (such as TSMC). This strategy is a better one for EDA vendors than not coordinating its new roles, and the most important part could be the definition of a decent straw man reuse methodology manual. Other EDA announcements included Cadence's "systems-in" verification strategy, and Avanti's "Galax!" services group. One wonders if some of the big suppliers are losing their focus on EDA technology and tools in their quest for rapid growth.

Synthesis Though lots of worthy FPGA and ASIC synthesis tools were displayed at DAC, the fact is that many industry observers were hoping for an "OK Corral" shootout between Ambit and Synopsys . Both companies did a professional job throughout and stayed focused on quality customer solutions. Ambit's demo suite was strategically positioned next to Synopsys 's and had constant activity from morning to late night. The buzz was that Ambit's marketing skills were as impressive as its new tool introduction, but Synopsys 's demos were very well attended, too. On the last day, I was witness to a very good-natured Synopsys executive agreeing to publicly wear Ambit promotional gear--in exchange for one of those nice Ambit clocks (détente in EDA?).

Verification and verification support Formal verification, which until this DAC seemed almost interchangeable with equivalence checking, grew into the model checking arena, with no fewer than four suppliers officially in the race. Lucent's FormalCheck was the big draw, but Verysys surprised many by showing model checking using the same Siemens technology and GUI used in the Abstract Hardware product (can you say "legal mess"?). Chrysalis demo'ed its multicycle symbolic simulation analyzer, which clearly reaches into the model checking space.

Cycle-based simulation continued with reasonable growth. The only real advance came from Top-Down Technologies, makers of Cyclops. Cyclops accepts everyday RTL code and compresses the events down to cycle boundaries. The resulting code runs on any HDL-based event simulator, with a 33 to 53 speedup or better. Note that its gate-level technology was exclusively OEM'ed to Mentor, making Mentor's QuickHDL-XLC product possible. The gate-level product speeds simulation 103 to 503.

The biggest news in emulation was that Synopsys is abandoning the Arkos product line and transitioning customers to Quickturn. The other recent news of interest was Ikos's emulation product entry based on the VirtualWires technology acquired from Virtual Machine Works last year. Ikos's Avatar is an enhancement of the VirtuaLogic emulation system, based on standard FPGAs, allowing earlier integration into the design flow. Quickturn featured CoBALT, its newest product for processor-based emulation using the "broadcast interconnect" architecture.

One of the few new twists in event simulation came from FTL Systems, the developer of parallel optimizing compilers for shared-memory multiprocessors, message-based parallel processors, and networked computer systems. Its Auriga product supports large-scale design capacity and high performance with full VHDL language fidelity and boasts an open-standard compiler-simulator interface (called AIRE). Expect to see Auriga bundled with some advanced simulators in the near future. Another twist came from ICL, which released its VHDL+ language for public review. VHDL+ adds some advanced system-level hardware implementation features but compiles into IEEE-standard VHDL for simulation.

Hardware-software co-verification is clearly a major issue, but not much breakthrough technology has appeared to solve it. Power estimation and power analysis tools were also more prominent, but again there is little fundamental change. I'm aware that EDA suppliers have substantial R&D work going on in both areas that should pay off in another DAC or two.

Timing verification hasn't advanced in any significant way either. Synopsys , though, made a big splash announcing its PrimeTime static timing analyzer. PrimeTime uses the new STAMP modeling language to handle complex cells such as memories and also uses part of the new CHDS-based API (inherited from IBM), along with technology for on-the-fly and more accurate timing calculations.

Most of the new verification support tools fall into one of two classes: code coverage analyzers or testbench generation and management. Such companies as 0-In, InterHDL, and TransEDA help users to generate more efficient, useful testbenches that cover more of the design. Verisity is a relatively new company that uses its own testbench language ("e") to specify tests from an architectural perspective. The e input is used to guide automatic test pattern generation and to monitor simulation runs with metrics, graphical verification analysis, and excellent coverage reports.

Deep-submicron effects Of course, deep-submicron (DSM) issues provided fertile ground for new EDA tools, as they have in recent years. This year, parasitics, reliability, and signal integrity tools gained momentum, in particular Lucent's upcoming tool set with a fully compliant CHDS interface. One stir was created by Frequency Technology, who claimed that its 3-D interconnect characterization approach "breaks the interconnect barrier." Its Columbus parasitic extractor refers to a library of primitives, each of which has been accurately characterized using 3-D field solvers. Simplex Solutions also received a lot of attention, offering (limited) signal integrity analysis along with an interesting variable halo region approach to bounding error on extraction.

Overall, new DSM effects, such as signal integrity and reliability, are being taken seriously by only a handful of EDA vendors, mostly start-ups with new algorithms and some venture-capital funding. Yet those effects will require more integration into the full flow, certainly all throughout physical design. The major EDA players have chosen instead to chase the IP reuse money train, leaving an integration hole. I expect that we'll see the leading technology customers--semiconductor companies--resort to close partnerships with the small vendors (because they understand the silicon issues the best) and also pull more development back in-house.

At its industry forecast, Dataquest anticipated rapid growth in semiconductor and system companies to propel EDA companies into the 23 to 40 percent annual growth range at least through 2001. Dataquest went on record by stating that the 40 percent target was predicated on achieving five specific system-level integration (SLI) goals: (1) completing the new RTL methodology tool set, (2) completing a new physical verification tool set, (3) defining the Virtual Socket Interface, (4) introducing a new system-level language, and (5) completing system-level macro testing. I agree and will clarify that item no. 1 refers to industry adoption of RTL interoperability standards, no. 2 refers to the CHDS-based concurrent tool flow architecture, and no. 4 refers to the new system-level design language (SLDL) standards effort. I'll talk more about each of those in upcoming columns.

In summary, the major EDA vendors are saying, "Show me the money" through IP reuse, and they've lost some sight of the EDA technology advances required to succeed with the DSM processes that make IP possible. The smaller EDA vendors are trying to fill those gaps, but they lack either the tool integration or the silicon knowledge of the semiconductor companies. Verification is being recognized as the biggest overall challenge, with hardware-software integration needs at the top, and formal verification is rising as the great white hope. Lots of IP suppliers have jumped into the ring, but the industry has yet to figure out what works, so a little bit of everything is being tried in the marketplace. *

Contributing editor Steven E. Schulz, P.E., is a senior member of the technical staff at Texas Instruments (Dallas).

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integrated system design  September 1997