Editorial

Cores and More Cores Designers must address paradigm shifts in their new methodologies. by Jonah McLeod

Having observed this industry for nearly 15 years, I've seen trends come and go--silicon compilation, frameworks, etc.--to cite a few. Today, yet another trend has arrived: reusable cores.

Unlike those trends of the past, reusable cores are here to stay, and designers should become proficient in using them as quickly as possible. One of the first lessons to learn about cores is the three distinct groups currently available--hard, soft, and firm. Each has their own benefits and drawbacks.

Hard cores are fully diffused blocks--the actual physical layout of a microcontroller, DSP, memory, etc. These are typically the property of large semiconductor companies, such as Motorola, Texas Instruments, etc. These devices are identical to packaged semiconductors, except they lack I/O pins and a package.

Typically, hard cores are available from the semiconductor company who owns the device or from a licensed second source. However, some smaller companies, such as Western Design Center Inc. (Mesa, AZ), offer them, as well. Furthermore, the block cannot be changed. It fits into an existing design in the same way a packaged IC fits onto a printed circuit board. During simulation, it appears as a black box with stimulus-in and response-out.

Soft cores are the opposite. They are typically owned by independent core vendors who create popular circuits and distribute them as Verilog or VHDL language files. Thus, the devices can be fabricated at any foundry. The files also come with testbenches. Since the files contain HDL statements, designers can synthesize the code along with other circuits being created from scratch. Some soft cores come as encrypted gate-level netlists. The file type, RTL or gate, will depend on the core vendor.

The drawback to soft cores is testing the circuit after it has been synthesized with other logic in the design. The testbench accompanying the soft core can test only the lone device. After synthesis, the testbench must be altered to verify the new logic, as well.

A firm core is a cross between a hard and soft design. It is a synthesized gate-level description of some function. Thus, like a hard core, the designer cannot change the circuit. However, the device is similar to a soft core because it can be simulated and placed and routed with the surrounding logic. It is also fab-independent.

If you are interested in learning more about cores, you should attend Design SuperCon97, January 21 to 23 at the Santa Clara Convention Center (Santa Clara, CA). There, Hewlett-Packard Co. (Palo Alto, CA) is sponsoring a project to evaluate designs containing cores. Attendees will see how designers are using cores to build a variety of different circuits.

If you are currently designing with a core and would like to participate in the competition, HP invites you to submit your circuit to a technical review team for evaluation by January 8. To qualify, the design must contain a 32-bit PCI core or a 16-bit DSP core. The core must be part of a larger IC design using a selected ASIC vendor library. All contestants will receive an HP scientific calculator.

The technical review team will recognize winners at a SuperCon panel on Thursday, January 23. Interested parties should contact Earl Reinkensmeyer at (970) 482-9677 or e-mail ERSummit@aol.com. Good luck and I'll see you there!

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  January 1997