Editorial

Trends In Deep Submicron Design Tools

The intricacies of the high-density, high-complexity designs create the need for more and better analysis tools.

by Jonah McLeod

As process technology advances below 0.35-µm feature sizes, designers will face a whole new group of design problems. These problems will demand engineers adopt new design flows if they are going to achieve successful results.

The floorplanner will become part of the front-end design flow. In addition, designers will be increasingly dependent upon back-end analysis tools to extract information on circuit timing, power use, and noise generation characteristics.

The new role of the floorplanner is to perform quick placement of gates and major blocks within a design. From this fast placement, the floorplanner extracts custom wireload models for all nets within the design and returns the backannotated netlist to the synthesis tool.

Using these more accurate wireload models, the synthesis tool reconfigures paths that contain timing violations. The resulting netlist is then passed on to the place and route tool for layout. The trend for the future is toward floorplanners that operate on the RTL netlist before synthesis occurs. Producing custom wireload models at the RT level will allow the synthesis tool to create an optimal netlist.

Gary Smith, principle analyst with market research firm Dataquest (San Jose, CA) has dubbed this trend "the RTL virtual prototype." The idea is to constrain an RTL netlist with information provided by back-end analysis tools so that the synthesis produces a netlist that is correct by construction. The types of constraints being fed forward would include timing, power, and noise.

The back-end tools providing this information are the new breed of extraction tools: timing, power, and parasitic extractors. Vendors of these tools include Avant! , Epic Design Technology, Frequency Technology, Sente, Simplex Solutions, Synopsys .com/isdweb/&If=isd-sendtolog"> Synopsys , System Science, Ultima Interconnect Technology Inc., and VeriTools.

The delay extractors, such as Avant! Star-R and Ultima-DC, compute the RC interconnect delays of a netlist. Epic, Sente, Simplex, Synopsys .com/isdweb/&If=isd-sendtolog"> Synopsys , System Science, and VeriTools produce estimates of power consumption based on circuit topology. This will help designers locate possible hot spots that could affect chip reliability.

The newer tools extract and model the 3-D parasitic effects of the complex topology of the interconnect network. The effects of the interconnect are particularly significant at the high speeds in today's ICs. In older tools, the extraction and analysis tools took too long to process the data. The problem is exacerbated by the large number of nets in system-on-a-chip ICs. Parasitic reduction tools now reduce the number of parasitics that need to be evaluated.

Another solution to the run-time problem is to produce more efficient algorithms. Ultima-3D is based on this approach. Ultima reports that a problem that took five days of computation with a true 3D solver was done in half a day with the Ultima-3D solver.

In the future, all of this extracted information will be provided to the floorplanner, which will then provide even more accurate custom wireload models to the synthesis tool. Only by providing tight links between back-end analysis tools and front-end floorplanners and synthesis tools will deep submicron designs be completed in a timely manner.

Jonah McLeod is editor-in-chief of Integrated System Design.

integrated system design  February 1997