Editorial

Verilog Evolves to Meet Designers' Needs Work on extensions to Verilog will improve designers' ability to develop system-on-a-chip ICs. by Jonah McLeod

There was a time when the design automation industry was about to write off Verilog as a dead language. That time has long since past. The language is not only alive, but growing as well, according to Maq Mannan, OVI (Los Gatos, CA) chairman and National Semiconductor's (Santa Clara, CA) director of design automation.

Mannan took over the reins of OVI from Bill Fuchs, whom drove much of the language's renaissance. Today, Mannan is touring the world, extolling the virtues of the future additions to the language. Next year will see the advent of Verilog 1364-1998 to replace 1364-1995. The new version will contain analog and mixed-signal extensions to allow simulation of these circuit elements, and it will also include digital logic and portable libraries, both beneficial for designers.

Analog extensions to Verilog will allow designers to simulate the behavior of analog and mixed-signal circuits with surrounding digital logic.

Verilog simulation is event driven--ideal for digital signals, but not for analog (which tends to be continuous and nondeterministic). Currently, analog stimuli are accommodated via the Programming Language Interface (PLI). The new extensions will simulate analog just as it would occur in an actual circuit.

Kim Halley, chairman of the IEEE study group, and his committee are on the verge of delivering a project authorization request (PAR) to the IEEE to make Verilog-A an IEEE standard.

"The portable library effort" is another aspect of Verilog standardization that is important to the average designer. Today, invariably, designers want to create a design in one HDL but may acquire IP in another HDL. Portable libraries will eliminate the problem.

Vassilios Gerousis, chairman of OVI 's Technical Coordinating Committee (TCC) and staff technologist at Motorola (Phoenix, AZ), is driving this effort. The idea behind portable libraries is to create a metalanguage in which all models can be described. The metalanguage description can then be interpreted by either Verilog or VHDL.

Gerousis says the general template has been defined by LSI Logic Inc. (San Jose, CA). The OVI team is implementing the various library modeling chapters. LSI logic is contributing the chapter on vectors, Cadence Design Systems Inc., the wire-load models, Viewlogic Systems Inc. , the functional description, Viewlogic's Quad Design Group, the power and timing table, Mentor Graphics Inc. , the equations, and everyone is contributing to the technology chapter.

Where both Verilog and VHDL need more progress is in defining a common synthesizable subset. The problem centers around how much or how little of its synthesis technology Synopsys .com/isdweb&If=isd-sendtolog"> Synopsys Inc. (Mountain View, CA) is willing to put into the public domain. ASIC suppliers and EDA vendors each have their own opinions and there is insufficient common ground to reach consensus.

To help advance a workable compromise, Integrated System Design has initiated a forum on this topic on its Internet home page, www.isdmag.com. Steve Schulz, one of our contributing editors, is making the case for the program technical advisory board (PTAB), Maq Mannan is arguing for OVI, and we hope to get a commentary from Synopsys .com/isdweb&If=isd-sendtolog"> Synopsys . Visit our Web site to see and hear these presentations, and then give us your opinion.

Jonah McLeod is editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  March 1997