Editorial

Finding Bugs Before They Become Bugs In Million-Gate Designs The verification of complex designs will require new tools to address interface problems. by Jonah McLeod

Ask anyone who designs circuits that have over a few hundred thousand gates and they will tell you that for every designer, there are two or more verification engineers on a project. Why are design teams spending more time verifying designs than creating them in the first place? The interaction between blocks in today's complex designs, creates fertile ground for growing numerous bugs. Finding these bugs has become a major problem that demands a large engineering effort.

For example, in the March issue of Integrated System Design , David Smentek and others of Hewlett-Packard Co. (Ft Collins, CO) claimed to have run over 100 billion vectors to verify the PA-8000 floating-point unit. This brute-force strategy to verification works fairly well, but it also absorbs an excessive amount of design time and compute power. This strategy requires that verification engineers develop test cases that can exhaustively test all error conditions, which is impractical for designing larger devices, because the number of possible errors increase at a faster rate than the number of circuit elements.

Furthermore, today's verification tools are designed to ferret out problems generated during the design process, not to locate bugs that result from a testbench. In many cases, the testbench relies heavily on existing tests for reused circuits.

In a million-gate design that uses multiple controllers and state machines--some reused, some designed from scratch--interaction between the elements is largely ignored by existing verification techniques. Applying emulation to the problem addresses some of the interaction problems. However, even exhaustive emulation can miss bugs, such as the infamous floating-point error found in an early version of the Pentium processor.

With the advent of designs containing several million gates, new verification techniques are needed to reduce the chore of design verification. David Dill and Mark Horowitz, two professors at Stanford University (Stanford, CA), are developing some promising techniques. The thrust of the Stanford research is to classify design bugs into several groups, then design tools best suited to find bugs in each group.

One group of bugs targeted by the university's research occurs in the interaction between larger cells of a complex design. To address this problem, the tool being developed at Stanford looks for bug precursors. For example, it checks if a status flag in one cell gets set by a second cell, and then set again by a third cell before the status flag is ever checked by the first cell. The technique also looks at HDL code that does not immediately lead to an error condition but does not have any immediate purpose.

In effect, the tool examines the HDL code for design intent. Once the intent is determined, it uses rules to evaluate whether the HDL code is actually serving that intent. The tool queries the code to determine if a potential bug can occur if triggered by the right set of events.

Another benefit is that the tool can be easily used with newer cycle-based simulators. In combination, the two promise a boost in verification effectiveness on complex, million-gate designs. Look for a new company to commercialize this technology and bring it to market within the next couple of months.

Jonah McLeod is the editor-in-chief of Integrated System Design.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

integrated system design  May 1997