Editorial

Silicon Compilation Strikes a Chord Support appears for a design methodology that looks like a revamped silicon compiler. by Jonah McLeod

In my last editorial I proposed the return of the silicon compiler. A couple of readers commented on the editorial, and a panel discussion that I recently moderated provided more comments about the desirability of such a product.

Richard B. Brown from the engineering school at the University of Michigan writes: "I agree with you that, for a number of reasons, the time has come for silicon compilation. We have been using Cascade's Epoch, and before it, ChipCrafter since 1986 at the University of Michigan. These tools have enabled us to do many research projects and have given students in our advanced VLSI course the chance to design large circuits, focusing on the high-level trade-offs where the most advantage can be realized."

David W. Potter from Lucent Technologies agrees. "I like the idea of an integrated path from floorplanning through synthesis to layout," he writes. "What would make your idea better and make tools more affordable would be acceptable standards for defining: synthesis requirements and performance, specifications, delay modeling, and fab design rules."

What the mainstream engineer is doing, however, is moving toward a design methodology that resembles the task that silicon compilers used to perform. This methodology was described during the panel discussion, when I asked the panelists what direction the integration between floorplanning and synthesis should take.

Panelist Michael John Sebastian Smith, a professor at the University of Hawaii, a member of the technical staff at Compass Design Automation, and the author of a new book titled Application-Specific Integrated Circuits , described a methodology that involves logic and physical design proceeding pretty much in parallel. "First you synthesize a small part of the design," he says. "The output is then turned over to a physical design tool for placement. The process is repeated with another part of the design until the entire circuit is completed."

Smith asserts that with this process the designer is incrementally decreasing the errors in his estimation of the delays as he proceeds. Today, in contrast, floorplanning occurs after the entire chip is synthesized. At best, the floorplanner can alert the designers to possible wiring congestion and help achieve timing convergence by moving blocks that are in a critical path closer together.

Starting with logic design and proceeding through physical design is a halfway measure, Smith asserts. With the advent of process geometries of 0.25 µm and smaller, designers are going to have to lay interconnect and then hang gates onto them. Doing that requires a floorplanner that is tightly integrated with a logic synthesis tool. The result is much the same as the silicon compilers of the past.

One such tool, Smith says, is being developed by Compass--now part of Avanti--Smith's employer when he's not teaching.

To hear the entire panel discussion, I invite you to listen in at our Web site, www.isdmag.com/dsm/, where we've posted it as a real-audio presentation. We've also provided a transcript for those who are audio-impaired.

In a separate matter, Integrated System Design surveyed its readers in July to determine how they were coping with deep-submicron design issues, and we plan to publish the results in the next issue. Please check it out.

One question we asked was how synthesis tools from Synopsys and its archrival Ambit Design Systems were meeting the challenges of deep submicron. One reader who requested anonymity provided us with a benchmark of the two tools. It will appear as a sidebar to the survey results. *

To voice an opinion on this or any Integrated System Design article, please e-mail your message to miker@isdmag.com.

integrated system design  October 1997