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Vendor corrects errors about built-in self-testing.

FEEDBACK


Dear Editor,

I was very disappointed to find several glaring errors in the Focus Report on design-for-test tools in the September issue [p. 36]. Specifically, the following paragraph is totally incorrect:

"But BIST is a functional test designed to ensure that a circuit runs correctly through a limited set of test vectors. It doesn't test the physical integrity of the device or provide insight into the operation of complex, indeterminate functions. For those capabilities, designers must look elsewhere."

Here are the facts:

  1. BIST is a manufacturing test, not a functional test.

  2. Its purpose is to catch manufacturing defects. That means that it is used to verify the physical integrity of the device.

  3. Unlike external testing or Iddq, BIST provides excellent insight into the operation of complex chips. LogicVision's BIST solutions are routinely used to test all on-board memories as well as all logic blocks. Additionally, because BIST is embedded within the chip, it provides a "dedicated channel" for gathering diagnostic information about the internal operation of the logic and memories.

  4. There is no limit to the number of BIST test vectors that are run, since they are generated "on the fly" by the on-chip BIST control circuitry. Most designers will select a high enough vector count to get the desired fault coverage (typically greater than 95 percent and often 100 percent) at the lowest possible test time.

  5. More importantly, LogicVision's BIST applies random patterns at speed for testing logic. Customer experience and research have shown that this approach yields higher-quality parts than the traditional ATPG approach. Specifically, at a given fault coverage, BIST-tested parts have a much lower rate of test escapes than the same parts tested using ATPG and an external tester. That's because the combination of random patterns and at-speed testing uncovers many defects that don't fit the standard stuck-at fault model, and that's precisely why BIST is so powerful at verifying the physical integrity of the device.

Bob Smith
LogicVision Inc.


Dear Editor,

"Top-Down Timing Design" in the July issue [p. 32] is the right article at the right time for us, because we're currently in the middle of evaluating timing design tools, such as WaveFormer Pro (talked about in the article) and TimingDesigner from Chronology .com/quickbench/isdpromo.html&lf=isd-sendtolog"> Chronology Corp. The article certainly can help us a lot, and many of the people here read it with great interest.

The magazine is doing a great job serving people like us.

Luke Chang
Fujitsu Nexion Inc.


Dear Editor,

I found the article on top-down timing design very informative. However, I would like to see more of a disclaimer about the authors. It's fine to give "free ad space" to vendors who write articles, but notice should be given up front that that's what you've done. Just stating at the end of the article that the person who has cowritten it is the vice president of marketing of the product used isn't enough. I wouldn't buy a product based on just one article, but I give more weight to a product that has been used by some engineer.

I can only guess (hope) that Bryan Hoyer used the product in a real design and found the product useful. That's my point: I don't know if he used it at all! I would bet that Donna Mitchell hasn't.

Sean D. Twomey
Pentek Inc.


Bryan Hoyer is indeed a user of the tool, but you're right to complain about vendors' marketers as authors or co-authors. That was a slip on our part.

Our policy is to publish articles written by engineers who are users, but sometimes there are appropriate occasions when an engineer at a tool or ASIC vendor is a co-author or writes a tutorial article.

--Editor

To voice an opinion on this or any Integrated System Design article, please e-mail your message to miker@isdmag.com.


integrated system design  November 1997



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