Programmable Notes

The Big Question in Counting FPGA Gates: Should Memory Be Included? But beyond that, is there a better way to measure capacity? by Larry Waller

Coming up with a logic gate count that most people can agree on surely amounted to a simpler task back in the '80s when gate arrays set the ASIC pace. Counting gates was a snap, because nobody challenged the classic array arithmetic to determine capacity: Four transistors always equal one two-input NAND gate. Ergo, 100,000 on-chip transistors produce a 25,000-gate array.

Early PLDs were easy too, since they were mostly simple devices. But it's a more challenging task with the new generation of programmable ICs, particularly FPGAs, that are zooming up the density scale. One reason is that architectures vary across the product landscape, consisting of many combinations of flip-flops, registers, switches, logic elements, embedded functions, and the like. In addition, they tend to have widely different interconnect and routing schemes that further complicate any kind of standard counting technique. Moreover, the architectures are hard to compare on an equal basis. Antifuse proponents (primarily Actel Corp. of Sunnyvale, Calif., and Quicklogic Inc., in neighboring Mountain View), for instance, insist that their efficiencies are twice that of SRAM-based devices, so that a 10,000-gate Actel FPGA would be equivalent to a 20,000-gate programmable device from Altera Corp. (San Jose).

The gate count picture is further convoluted by the multifunctional devices that represent the most promising products coming onto the scene. All include some kind of memory On-chip memory is a useful feature, but it poses perhaps the knottiest density-measuring problem, because memory gates have to be totaled in a different way than logic gates.

This issue is an important one too, because device capacity, in terms of gate count, is high on the list of programmable features being hawked by marketeers. Having the highest gate count never hurt any vendor in winning the hearts of equipment designers who require devices of at least 20,000 gates.

Bragging rights flowing from high-capacity programmable ICs are therefore based on a solid need. This reality makes the gate count issue one of continuing importance, despite the contrary opinion of some PLD execs who hold it to be essentially a "gate array ball game we can't win." Craig Lytle, director of product planning and applications at Altera, expresses the majority view, saying, "This is disingenuous, ignoring gate count." He regards gates as a comfortable metric for designers to use in evaluating programmables, so that gate counts will continue to be widely followed and used regardless.

Indeed, Altera has done the most to influence the industry on how to count logic gates and integrate memory size into gate totals. The company preempted the early debate on this topic in 1995 by issuing a paper on gate-counting methodology and introducing the Flex 10K family of CPLDs with embedded logic and memory. The company's basic building block is a 12-gate "logic element." This metric gets little argument, but translating embedded RAM into equivalent gates arouses debate, Altera concedes, because it amounts to a highly subjective calculation. The majority view, cited by Altera, is four gates per memory bit, which is what the company uses.

Xilinx Corp. (San Jose), one of Altera's biggest competitors, leads the opposition. It firmly believes memory is something that should be treated differently, as a category "to be broken off separately, not to be included in gate counts," says David Squires, product marketing manager for high-density FPGAs. "Altera's method is very confusing to customers. We need something more objective, something that doesn't get lost in concentrating on this gate obsession, which has evolved over the years. After all, gates are just the brick and mortar," he adds. To counter Altera, Xilinx produced its own benchmark white paper, "An Alternative Capacity Metric for Look-Up Table (LUT) FPGAs," early this year.

Xilinx believes that by dealing with the basic logic building blocks that make up every FPGA, it can measure capacity better. The common metric, a "logic cell," is the combination of a four-input lookup table and a dedicated register residing in the same block, Xilinx says. As a point of interest, this metric is nearly identical to Altera's for counting the logic portion of FPGAs. Altera's basic block in the Flex10K architecture is a logic element that contains a four-input LUT and a programmable register.

Using its definition makes possible simple capacity comparisons between equivalent devices, Xilinx points out. Examples are its XC5000 family and the ORCA 2C FPGAs from Lucent Technologies Inc. (Murray Hill, N.J.), each with four logic cells per array element, and the Altera Flex with eight logic cells per element. With this approach, Xilinx's technique can expose "the inconsistencies of the various manufacturers' claimed gate counts," the paper says. For instance, Altera's 10K40 device, with its 40,000-gate claim, and Lucent's 2C26, with 26,000 gates, both have 2,304 logic cells, slightly fewer than Xilinx's XC4025E, which the company says has 2,434 cells. (Xilinx's competitors take issue with this comparison, saying that the company gives itself an extra 0.375 gate/cell edge in the conversion from cells to gates, but they concede that the devices are actually nearly equal in capacity, whatever the marketing claims.)

The Altera-Xilinx gate count debate generally serves as a framework for the competition to discuss the issue, picking and choosing what's useful in showing their products in the best light. Actel has taken several positions. When it marketed solely antifuse devices, the company line was that SRAM-based FPGAs were only half as efficient in using logic gates, so never mind the bigger capacities--that is, until it introduced its own SRAM-based embedded logic devices. Altera had already established its technique for accounting for the multiple functions, "so why fight it," says Robert Nalesnik, director of product marketing, "They're the pioneer, and we agree with them."

Other marketeers doubt whether the gate count game makes much difference, except to vendors pushing the big chips. Most users, even first-timers, know their general gate capacity needs in advance, so accurate gate counting "isn't a burning issue," says Andy Haine, a veteran programmable device executive. Now vice president for marketing at Synplicity Inc. (Sunnyvale), an EDA start-up, he notes that at this point users have a better idea of how to pick the right-sized programmable device than in the past. They can employ familiar synthesis design tools with a design need targeted to a specific device and get the right answer. Besides, arguing about who has the biggest programmables "will be a moot point for at least several years for a good reason," he says. "Nobody can do an accurate gate count until we have real designs on actual chips. Then we'll apply the recognized LSI Logic methodology [the LCA300K Data Book, cited by Altera and others] and we'll see."

Undue emphasis on big devices with large gate counts works against realism in users committing designs to the right-sized product, says Joel Rosenberg, marketing and applications manager for programmables at Atmel Corp. (San Jose). Studies he cites show that designers need only about 20 percent of a programmable chip's logic for most tasks, so much of the FPGA capability is wasted. "Capacity is more something that vendors go after each other on, rather than valuable information designers can use."

Although touting big-gate-count programmable devices will undoubtedly stay in the product headlines for the next several years, there is surprising agreement among many players that by the millennium it could be a lesser theme. The reason is that by then programmables will be so large--most sources predict at least 2 million gates by 2000--that their capacity limitations vis-a-vis gate arrays will be less important.

Also, as a product matures, the benchmarks by which it is described and judged change, just as happened with microprocessors nearly two decades ago. "Remember when the companies bragged about how many transistors their processors used?," recalls Atmel's Rosenberg, "That got lost as MPUs rightly became identified by what they can do. Transistor count is now only a curiosity. That will happen with programmables and gate counts as our functions rapidly expand." *

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integrated system design  October 1997