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Programmable Logic

Years of Strong Growth Lie Ahead for High-Density Programmable Devices

Experts agree that programmables have a rosy future, but some say standard cells could make inroads down the line.

by Larry Waller


Programmable logic shows such rosy prospects into the next millennium--a compound annual growth rate (CAGR) of more than 25 percent--that even bullish proponents can find little about which to complain. The principal market analysts support this upbeat consensus. Programmable growth rates not only lead the ASIC field but continue to outpace all IC products except for flash memories, according to Integrated Circuit Engineering Corp. (ICE; Scottsdale, Ariz.).

ICE foresees the hottest programmable devices, complex PLDs (CPLDs), achieving a 30 percent CAGR from 1996 to 2001. FPGAs will be close behind at 29 percent, both types well surpassing the average for all ASICs, which are growing at only 18 percent. Gate arrays, long the ASIC workhorse product, will continue to show a declining rate, dropping to only a 12 percent CAGR during the period.

ICE's market estimates also highlight the only other ASIC type cruising the fast-growth lane--standard cells. Some, like Dave Bostwick, vice president of Pathfinder Research Inc. (San Jose), believe that cell-based chips may have an important impact on programmables' bright prospects by cutting into their market. ICE sees these devices, propelled by the growth of "systems on a chip," achieving 27 percent compound annual growth through 2001. That would be a truly impressive performance because standard cells are growing from a 1996 market base of $6.1 billion, compared with $1.55 billion for high-density programmables.

Fueling the surge of both programmable and standard-cell devices are the demands that IC customers make on suppliers for ever more complex devices and faster prototype turnaround and production times. Each type targets a different end of the density spectrum. For the most part, programmables serve design-in needs up to the 50,000-gate range, with the average now running from 10,000 to 20,000 and climbing slowly. Standard cells, with their strong customizing feature­the choice of many predesigned functions on one chip­are about 10 times more complex in terms of density.

The two types also differ in prototype turnaround time. For programmable devices, the time is measured in hours, versus months for cell-based designs, although leading suppliers, such as LSI Logic Corp. (Milpitas, Calif.) and Lucent Technologies Inc. (Berkeley Heights, N.J.), have cut turnaround time to four to six weeks, and for premium prices some suppliers can do it in a week.

Putting on the squeeze As ICE's projections show, these hot programmable and standard-cell products are cutting steadily into gate arrays, as well as expanding their own user turf. "It's the bookend effect­programmable logic on one side and cell-based products on the other­squeezing out gate arrays in the middle," observes Mark Stibitz, vice president for integrated systems at Lucent. Stibitz directs both product lines for the communications technology company, which was spun off last year from AT&T Corp.

Lucent offers both programmables and standard cells, so its strategic view of these businesses is likely to gain considerable credence as the markets for both types grow. According to Lucent, the future favors the cell-based side, and Stibitz expects Lucent's future ASIC results to reflect this upward integration. Last year, its standard-cell revenues jumped 50 percent, to $960 million.

Stibitz emphasizes, however, that supercharged cell-based growth will not come at the expense of programmables and that Lucent will also make its mark as an important programmable device supplier. "But," he adds, "programmables will be in a different form than many people think."

Lucent sees programmables achieving their highest value as logic functions incorporated into cell-based designs. "The question is," Stibitz says, "Is a programmable a stand-alone product or a form of IP [intellectual property] to be embedded on a chip?"

Table 1
Selection criteria for different logic options
Criterion Standard components PLDs Gate arrays Standard cells Full-custom
Time to market Short to medium Short Medium Medium Long
Development lead time Immediate Immediate Weeks to months Weeks to months Years
Development cost None Low Medium to high Medium to high Very high
Availability High High Medium Medium Low
Available sources Many Many Few Few Few
Volume dependence Low Low High High High
Application support Much Much Some Some None
Architectural flexibility Low Medium to high High Higher Highest
Design change ease Medium Medium to high High Higher Highest
Performance Low to High High High Very high
Density Low Medium Very high Very high Very high
Solution efficiency Low to Medium Low High High Very high
Design change cost Low Medium High High Very high
Source: Integrated Circuit Engineering Corp.

Atmel Corp. (San Jose), another company with operations in both programmables and standard cells, has a similar view. The company sees the emergence of hybrid system-level chips in which a portion of the silicon is dedicated to hard cores of standard functions (much like a cell-based ASIC) and another portion is an FPGA, says Joel Rosenberg, director of FPGA marketing (see "The potential for IP"). Standard products could include such IP as DSPs, microcontrollers, UARTs, and PCI cores embedded in the silicon, combined with standard FPGAs of varying densities. Only about 20 percent of a typical design requires customization, he says, while the other 80 percent is standard functionality.

Rhondalee Rohleder, formerly a principal at Pace Technologies in Scottsdale, Ariz., and now director of strategic marketing at QuickLogic Corp. (Sunnyvale, Calif.), also believes that mask- and field-programmable device types will be used on the same chip. "But it's a question of degree and will take longer than people think, well beyond 2000," she says.

Any scenario that negatively affects programmable growth attracts attention from the dominant suppliers, Altera Corp. and Xilinx Inc. (both of San Jose), which between them control more than two thirds of the business. Neither company sees a chance that devices combining the two products will make meaningful inroads into programmable territory. The hybridlike devices, they say, would have high custom-product type prices and would damage the fast time-to-market feature that programmables offer. On this issue the two companies are in rare agreement.

Leaving that issue aside, ASIC success will depend on having both products in-house, Lucent maintains, and "you could see some interesting things happening" in terms of alliances and mergers, Stibitz predicts. The FPGA vendors who already have access to core technologies for processors, memory, ASICs, and programmable logic will be in the best position to offer a system on a chip with the flexibility of programmables and the cost-effectiveness and performance required by the market, Rosenberg agrees.

Table 2
High Density PLDs and FPGAs
Company Device family Density range (usable gates) Highest density available
Actel 3200DX 6,500-40,000 20,000
Altera Flex 10K 10,000-100,000 100,000
Atmel AT6000 2,000-20,000 20,000
Cypress Ultra38000 7,000-20,000 12,000
Gatefield GF100K 9,500-100,000 51,000
IBM Series 10000 8,000-42,000 16,000
Lattice ispLSI 6000 up to 25,000 25,000
Lucent ORCA Series 4,000-60,000 40,000
Motorola MPA1000 3,500-22,000 22,000
QuickLogic pASIC2 3,000-20,000 20,000
Xilinx XC4000 28,000-125,000 52,000
Note: The density range and the highest density available are as of mid-1966.
Source: Integrated Circuit Engineering Corp.

Different businesses But both Altera and Xilinx reject the idea of one vendor offering both types of products. "These are fundamentally different ways of doing business," says Bob Beachler of Altera, until recently director of strategic marketing and now director of development tools marketing. Bringing a standard-cell operation into a programmable company would make no sense, he adds.

The potential for IP
Among the new opportunities on the programmable horizon, probably the most intriguing is how fast predesigned core functions, or IP, will develop as an important business.

Silicon suppliers and independent vendors offer these cores in design libraries or as separate products, but a knotty problem is hampering growth: the lack of standard formats and interfaces that make it possible to port cores easily and successfully to different ASIC vendors.

To undo the knot, last year design industry leaders launched the Virtual Socket Interface Alliance (VSIA), which quickly received the active support of more than 135 EDA vendors, IP suppliers, chip makers, and system manufacturers. Its goal is ambitious: to allow chip designers to use cores from multiple sources to create a chip any manufacturer can produce. All parties acknowledge that the alliance has a tough job to write the design and process compatibility standards, along with solving licensing and royalty issues. But things are coming together so well, its officials report, that initial standards will be delivered this year and nearly completed by the end of 1998.

Opinions vary, however, on how fast the IP business will grow from virtually zero in 1996. Some market analysts, such as Handel Jones, president of International Business Strategies (San Jose), predict a $2.5 billion IP programmable share in 2000, while Rhondalee Rohleder, formerly a principal at Pace Technologies in Scottsdale, Ariz., and now director of strategic marketing at QuickLogic Corp. (Sunnyvale, Calif.), warns that success of that magnitude will take far longer.

The programmable market heavyweights also take a cautious stance. Sandeep Vij, vice president of marketing at Xilinx Inc. (San Jose), for example, judges IP as "still in its infancy," and Bob Beachler, until recently director of strategic marketing and now director of development tools marketing at Altera Corp., also in San Jose, says that his company anticipates revenues from IP-based chips early in the next decade at only the level of its software products, or approximately 6 percent of sales.

Sandeep Vij, vice president of marketing at Xilinx, concurs. "There will always be a significant difference between programmable ASICs and standard cells."

Both officials point out that standard-cell vendors sell a customized product to a small clientele, while programmables are flexible standard products going to many designers. "Trying to mix them would be the worst of both worlds rather than the best," Beachler says.

On the programmable versus standard-cell question, which appears likely to generate controversy as the two products compete more directly, other market consultants are waiting "to let the market sort it out as it always does," says Brian Matas, market analyst at ICE. Meanwhile, the potential programmable market is so huge that high-density programmable growth will not miss a beat for any foreseeable cause, QuickLogic's Rohleder predicts.

Whatever the timing and outcome of this issue, the upward programmable sales path is clearly marked, as CPLDs and FPGAs bag more users with their demonstrated advantages. CPLDs provide an inexpensive way to integrate simple PLDs, and FPGAs support expanded functionality as gate counts exceed the hundreds of thousands of gate equivalents. They continue to give system designers better flexibility, performance, and fast time to market while meeting improved product requirements, ICE says. While the two types compete for the same board sockets, they often complement each other through their differentiated architectural features. CPLDs manage control logic better, whereas FPGAs are superior for implementing fast datapaths.

These high-density PLDs--what Rohleder calls "HDPLDs," defined as having more than 40 pins--account for up to 80 percent of PLD sales, Rohleder estimates. Premium products, they are used mainly in four rapidly growing application areas, split between telecom and data comm--PBXes, wireless communications, local-area networks, and ATM equipment--where they're employed extensively in routers and switches that transmit data across networks. Connecting two networks with different protocols demands the immediate reprogramming turnaround that is possible with FPGAs, for example, because the standards evolve so quickly. The value of programmable devices, especially for the low volume applications--1,000 to 10,000 units in most cases--is the ability to make rapid changes to the hardware when competing solutions, such as software-programmed microprocessors, can't fill the time-to-market bill or meet performance requirements.

Standards becoming established The encroachment of standard cells into what is now programmable territory could happen as it plays into another trend, notes Bostwick of Pathfinder Research. Communications equipment is settling down to the point that standards are being established. Solid standards mean that instead of using programmable devices, which are expensive in high volumes, to produce hardware to accommodate rapidly evolving protocols, communications equipment suppliers could instead look at optimized ASICs, such as standard-cell devices with less expensive unit prices, to replace them. "That doesn't mean imminent disaster for programmable vendors, but it is something to look out for long term," he says.

A cost model developed by International Business Strategies (San Jose) illustrates why FPGAs are believed to be limited to low volumes, such as the communications equipment slots. Based on equivalent gate counts, 5,000-part production, and a $30,000 NRE for gate arrays, the programmables are cost-effective only up to about 10,000 gates. Above that, they take a beating on a cost-per-unit basis from gate arrays, which also can be more optimized for a specific application, says Handel Jones, president of IBS. But the market is demonstrating that this model is flexible--the growth of programmables proves that other factors often carry more weight than cost analysis. Meeting market windows, and therefore sales and profit goals, appears to be tilting design decisions toward both FPGAs and CPLDs, even when unit costs are two to three times higher than for other ASICs, suppliers believe.

So far, few high-density programmables of either the CPLD or FPGA variety have been converted into gate arrays, largely because product development and life cycles are moving too fast. Also, the design conversion packages offered by silicon vendors don't perform efficiently. However, newer solutions are arriving that promise improvements using common HDL design techniques to bridge the conversion gap between PLDs, standard cells, and gate arrays.

Xilinx's Vij insists that any cost advantages from converting to cell-based designs from programmable devices would be illusory. One reason is that programmable prices are dropping faster than ever with the onrush of smaller device geometries. Another is that the rapid evolution of equipment designs keeps customers from tackling the difficult task of converting programmable devices into other ASIC types.

Market seers and company officials express little doubt that the PLD business will grow to between $5 billion and $6 billion by 2001. HDPLDs should get the lion's share, at $5.1 billion, with simple devices barely a blip on the radar screen at about $150 million, according to Pace Technologies.

Industry observers don't foresee a repetition anytime soon of the conditions that triggered the 1996 growth downswing. HDPLDs increased 21 percent for the year, far below the 1995 rate, and all PLDs grew only slightly more than 12 percent, Pace Technologies reports. Analysts say that double ordering and long lead times of up to 20 weeks, spurred by communications equipment customers, led to a severe inventory buildup that took nearly a year to work off. But the recent strong demand by the communications internetworking market for PLDs has put them back on the growth path for years to come, Pace predicts. *

To voice an opinion on this or any Integrated System Design article, please e-mail your message to miker@isdmag.com.


integrated system design  October 1997



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