System Design

Managing Power in Million-Device IC Design

A complete system approach for microprocessor design includes power analysis.

by Ken Munson

In recent years, power consumption has become an important IC design consideration. For portable systems, reduced power means longer battery life, fewer and less-expensive cooling requirements, and use of lightweight IC and systems packaging. For high-performance microprocessors, power minimization is crucial for avoiding reliability problems, such as electromigration and voltage drop, and can increase the processor's value for mobile applications.

For these reasons and more, many designers now include low power consumption as a primary design criterion. A few years ago, we could often design an IC without taking any power-reduction measures and be within 80 percent to 100 percent of our power goal. However, lower power goals, combined with increased size and complexity, have made power management essential but also more challenging.

RISE Technology (San Jose, CA) designs large, complex microprocessors for the compatible market. We take a "complete system" approach to our designs, considering all potential improvements in terms of performance, power consumption, and system design. We implement features that will, combined, give us the performance we desire, minimize power dissipation, and ease the systems integrator's use of our processor.

We recently designed a new multi-million-transistor microprocessor that potentially will be used in applications ranging from fan-cooled office products to the smallest ultra-portable products. We needed to design one processor that would work in any of these environments, and although it is not expected to be used exclusively in mobile products, low power was a primary design concern, along with size, performance, and schedule.

The power-management design methodology used for this microprocessor is characterized by two phases. The first phase is proactive, where we anticipate and address sections of the design expected to consume the greatest amount of power. This phase involves high-level and implementation-level design decisions to reduce power. In the second phase, we analyze all sections of the design. We identify the areas where power consumption is greater than expected and make adjustments to reduce power in these sections.

Phase 1: proactive power management
The following is the equation for power:

power = frequency x capacitance x voltage ²

Voltage has the greatest impact, but it is dependent on the technology used and cannot be modified through design decisions. While considering voltage reduction is good, it is not aggressive enough for today's power goals. Designers must do more.

The next major contributor to power consumption is switching activity, which is reflected in the frequency. This area is where we focus many of our first-phase power-management techniques. By reducing the number of times devices switch, we can reduce the design's overall power consumption.

Size caching structures properly One technique for managing power at a high level is to determine the proper size of caching structures. Rather than considering only area versus performance, power should be included as the third factor on which decisions are based. No formula exists for determining optimal size, so it is necessary to determine the caching structure's characteristics, and to consider the performance and power consumption you can get for various sizes and numbers of associativities. For example, a size increase may improve performance but worsen power, so you must decide if you need that performance. If the performance gain is small, but the power increase is large, this may not be a good tradeoff.

Figure 1. The first phase of RISE's low-power methodology takes a proactive approach. Power-saving techniques are used at the architectural level as well as the implementation level in those areas expected to consume greater power. Power analysis helps confirm the savings achieved.

Eliminate speculative reads when possible Speculative reads involve interrogating a caching structure every cycle because you may need the results (although much of the time you do not). One technique for minimizing power is to read a caching structure only when necessary (see Figure 2). From a high-level design point of view, you want to interrogate these structures only when necessary to maintain performance and avoid a size increase. Eliminating speculative reads is a technique that you must use carefully so as not to have a significant impact on performance. You must make tradeoffs.

The important thing to remember with this technique is that results will vary according to the caching structure's characteristics. For example, in our design, we eliminated most of the power consumption of a specific caching structure--with little performance loss--by eliminating speculative reads. However, there were other caching structures where we achieved more modest savings.

For our multi-million-transistor design, we began with a high-level analysis to determine where we were with our frequency targets and what voltage we could use with our technology. Given the voltage (which is pre-defined) and speed of each device at that voltage, we partitioned and defined our high-level structure, considering where we could include these two power-saving techniques (caching size and speculative reads).

Once we completed the architectural-level definition, we began implementation.

Design implementation In addition to the high-level power-reduction techniques discussed above, we also used several design-implementation techniques:

2. Provide unchanging inputs for sections that must be clocked. In some instances, there may be a section that is not used but must be clocked continuously, just in case it is needed. This is because the slight delay in restarting the clock causes unacceptable performance degradation. The key to managing power for such sections is to provide unchanging inputs, so that even though the latches that receive the clock are clocking, the logic cones they feed are not switching (and consuming power) because the data is not changing. Take, for example, a large adder. If the adder is continuously adding zero and one, the logic in the adder is not changing from cycle to cycle. The adder's inputs come from latches that must be clocked at certain times, but if we know that we don't care about the results of this adder for several cycles, we can zero out the inputs, and while the latches may be clocking, the zero keeps going into the adder, and the adder won't switch.

Figure 2. This shows how the power consumption of cache structures varies when different high-level power-reduction techniques are applied.

4. Enable power and data only when needed. Certain structures, because of their usage characteristics, can be disabled most of the time. Other structures must be accessed often, but selective enabling of only the data outputs required can reduce these structures' power consumption 20 percent to 50 percent. For example, our design had a structure that produces 32 bytes of data, but we needed only four. With proper selection of the structure's outputs, we could read out only the four bytes required, saving the power that would have been consumed reading the additional 28 bytes.

Figure 3. PowerMill usage methodology encourages power budgeting. Analysis of the blocks which violated the power budgets can be performed to check if they have excessive short-circuit current or glitches.

With our multi-million-transistor microprocessor, we implemented these low-power techniques in areas where we expected higher power consumption. Power analysis, using PowerMill from EPIC Design Technology (Sunnyvale, CA), then helped determine whether specific approaches saved power without performance loss, or whether the given approach didn't save much at all. PowerMill allowed us to do a block-by-block analysis and to find areas of high power consumption before going to silicon (see Figure 3).

PowerMill analysis requires a netlist (in Spice, Verilog, EDIF, etc.), either from synthesis or extraction. It also requires data patterns (vectors), which the engineer must provide. Developing these patterns is key to effective power analysis.

Because our designs are so large, power analyses are run on sections of them rather than on the whole design simultaneously. Each section contains logic plus multiple inputs. To accurately simulate a section's power consumption, we must continuously drive inputs, toggling with patterns that will cause the logic, including memory elements, to change states. When the IC is operating, the transistors will not all switch simultaneously--they will switch in a pattern. So, to simulate power consumption under true operating conditions, it is necessary to run patterns similar to those that will actually occur.

A regular caching structure, for example, has regular inputs, and the data patterns are easy to develop. You can also test everything on this kind of structure by working through all the combinations of reading and writing every address to see what power is over time. By comparison, the standard logic patterns are more difficult. They must test the high end of power consumption. For standard logic, we may come up with tests that exercise all the chip's facilities as much as possible. Or, for an estimate of typical power, we might use a fragment of a characteristic application.

Once we develop these patterns, we feed them into PowerMill, along with the netlist. The results tell us how much power we saved using the previously described techniques.

With this particular microprocessor, we knew our power goal was aggressive and that a combination of all the techniques would be required to meet it. We did a first pass of the design, implementing our low-power techniques and methodology, and then ran PowerMill on it to tell us how much power we'd saved.

Figure 4. High-power usage is identified so that additional measures may be taken to reduce consumption in these areas.

Each of the power-saving techniques used has some complexity, which adds logic. If implemented incorrectly, you can add power instead of saving it. For example, in partitioning a design into different clock domains, it's tempting to think you can minimize power by having dozens of different clock domains. The problem with this approach--especially with a microprocessor as large as ours and running at such a high frequency--is that clock skew must be minimized and doing so means the clock structures for each clock domain must have the same timing characteristics. If you make your domains too small (say, for example, you define a domain with only 20 latches in it), the overhead for adding that extra clock domain can consume more power than you are saving. With PowerMill, we could quickly tell whether we'd saved power or increased it.

Phase 2: validation of power-management design PowerMill also provided a second--and perhaps more important--form of feedback. PowerMill's diagnostic capabilities highlighted all of the high-power-consumption areas, making it easy to identify areas where we could use additional power-reduction techniques. In some cases, PowerMill helped locate hot spots that would not otherwise have been obvious. For example, although an area may not be consuming excessive power, it may be consuming more than is required (or expected) for the contribution it makes to the processor's performance. Once these spots were identified, we implemented the techniques described to further reduce power consumption.

In this second phase of power management, we used PowerMill to identify the high-power areas not addressed in Phase 1. Armed with knowledge of where the design could be improved further, we made more power-saving adjustments, re-ran PowerMill, and determined whether we had further reduced our power budget.

Conclusion Low power consumption is increasingly a primary design criterion, and our design group constantly strives for the optimum mix of performance, power dissipation, and ease of integration. We have found that certain architectural decisions, coupled with several design-implementation techniques, provide the power savings we need. These methods share a common approach of reducing power by decreasing switching activity. By powering logic structures only when needed, you can significantly reduce a design's power consumption.

Ken Munson is principal engineer with RISE Technology. He is responsible for designing RISE's microprocessors.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@asic.com.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

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integrated system design  May 1997

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