Design for Test

The Seven Deadly Sins of Scan-Based Designs

This article may be your DFT salvation. Scan-based design in ASICs requires
attention to certain design techniques.

by Benson Cheung, and L. T. Wang

Scan-based designs provide high fault coverage, but several design structures hinder the ability to test for manufacturing defects. In designing for test, designers should try to avoid using those structures. When they're unavoidable, alternative techniques should be used to circumvent test problems to improve fault coverage.

Nothing is without a price, though. Implementing scan means the use of scan flip-flops that are larger than the flip-flops typically used for logic, so there is an impact on area. Peformance, too, can be affected, because of the multiplexers in the scan flip-flop datapath. However, the performance penalty can always be considered during synthesis and can thus, in theory, be eliminated.

Figure 1. Inserting the OR gates converts the SR latch from a function with ambiguous outputs into one with known states for testing.

Adhering to the design-for-test (DFT) rules discussed here will help make scan successful, allowing designers to improve the quality and yield of their IC designs. In addition, several test design automation tools can help the designer improve testability.

To create a scan-based design that achieves high fault coverage, today's designers must devise a flexible DFT methodology that limits or even eliminates the use of SR latches, D latches, combinational feedback loops, gated clocks, derived clocks, sequentially controlled asynchronous set or reset, and bus contentions.

These design structures, which we have dubbed the "Seven Deadly Sins of Scan-Based Designs," can render a chip untestable and unmanageable. In the long run, you'll burn in Designer Hell if you use them.

The temptation In scan-based designs, memory elements (latches or flip-flops) in a circuit are replaced with their equivalent scan parts. The equivalent parts have two data inputs. Normal functional operation uses one input and the memory elements use the other to form a chain of shift registers called a scan chain. The Scan-Enable of each scan flip-flop is used to control which input is selected and is automatically controlled by the test patterns during testing. The scan chain enables logic values to be directly applied to the inputs of the combinational logic and the outputs to be captured so that the outputs can be scanned off the chip and compared with the expected values on the tester.

This type of scan chain allows for the use of fast combinatorial ATPG (automatic test pattern generation) tools. There are many well-established algorithms for generating patterns for combinational logic, and several commercial products are available.

The scan chain in a full-scan methodology includes all the memory elements found in the design. In designs where area or timing constraints make it impractical to include all the memory elements in the scan chains, designers must select a subset. Such designs are called partial-scan designs.

Figure 2. Adding a scan latch and a multiplexer allows a feedback loop to be opened for testing.

As previously mentioned, memory elements in the scan chain can be latches or flip-flops. Latches are scanned using the level-sensitive scan design (LSSD) methodology, invented by IBM. Although this approach prevents timing problems, it is very area-intensive, since most designs are based on flip-flops and their scan chains need to use the large scan flip-flops.

Sins and salvation Including the following structures in a design can seriously reduce the effectiveness of scan. The structures prevent the scan chain from properly shifting patterns in, and they make it virtually impossible to generate test patterns. Ideally, designers should try to omit all of these structures from their designs. However, if that isn't possible, they can use "work-arounds," which unfortunately have two drawbacks: They add area to the design, and they affect timing.

Figure 3. Gated clocks require either an additional gate to enable the Clock or Test Enable signal (Solution #1) or a multiplexer to select between test and gated clocks (Solution #2).

SR latches Designers use SR latches to reduce the number of gates in a design. These latches are simple to implement, and they are an inexpensive way of creating a latch. However, they cause testability problems. SR latches are sequential elements, so that when both inputs of the cross-coupled NAND gates are 1, the latch's output remains the same as the previous state. They are therefore difficult to test with combinational ATPG.

Therefore D latches should be used instead. However, if SR latches can't be avoided, it is possible to make the circuit testable by making each of the gates behave like a buffer or an inverter during testing. Inserting two OR gates converts the untestable SR latch into a set of separate gates (see Figure 1). When Test Enable is set to 1 during testing, the circuit converts the cross-coupled gates into two inverters.

D latches Latches can't be scanned unless they are converted into scan latches. Unfortunately, conversion creates an extremely large area overhead. If the latches are part of an embedded memory, they can be modeled together as a memory, and using a memory model can reduce the difficulty of generating patterns for faults near the latches. However, special tests are required for the latches.

When latches aren't part of the memory, a more general solution is to make the latches transparent during test mode. To make the latches transparent, add an OR gate in series with the clock input so that one input is the regular enable signal and the other one is the Test Enable input. Doing so takes care of the problem of propagating fault effects through the latches, but the faults on the latch enable logic are completely untestable, reducing fault coverage. The best solution is to avoid using latches.

Combinational feedback loops Combinational feedback loops introduce sequential behavior into otherwise combinational logic, making it difficult to use combinational ATPG tools. In addition, such loops may lead to races and hazards, resulting in unpredictable circuit behavior. These loops are generally delay-dependent and therefore can't be tested with any ATPG algorithm.

Figure 4. Testing derived clocks requires the use of a multiplexer to bypass the division stages.

Typically, designers will omit combinational feedback loops from their designs. However, the loops can be created unknowingly when two portions of a design done by different designers are tied together.

If creating combinational feedback loops is unavoidable, designers should add test logic to the design (see Figure 2). This fix allows combinational feedback loops to be broken during testing by using a scan flip-flop.

Gated clocks Two common types of internally generated clocks are found in an IC--gated clocks and derived clocks. A gated clock is generated from an external clock and goes through at least one combinational gate, as well as buffers and inverters. Designers often use this type of clock to reduce the power consumption of an IC by temporarily turning off part of the circuit when it's not in use. Unfortunately, the clocks of these flip-flops can't be controlled from primary inputs, making it impossible to scan in data. Removing the flip-flops from the scan chain is one solution, but doing so often results in a loss of fault coverage. If designers can't omit gated clocks from a design, they have two options. One is to add an OR gate at the Enable pin so that the external clock can be connected to the flip-flop's clock input; the other is to multiplex the data with the flip-flop's output (see Figure 3).

Derived clocks A derived clock is generated by a flip-flop, latch, or any internal clock generator (such as phase-locked loops, frequency dividers, or pulse generators) in the circuit. Derived clocks can render a large part of the design untestable, because the flip-flops aren't controllable from any primary input. The lack of controllability makes it impossible for designers to scan in values.

If designers can't omit derived clocks from a design, they can address the testability problem by adding a multiplexer in front of the clock pins (see Figure 4). If a multiplexer is already used for selecting different derived clocks, its functions can be expanded to handle one more clock input coming from a primary input. This solution not only eliminates adding a multiplexer, but also the timing problems it could cause.

Sequentially controlled asynchronous set or resets Scan operations can activate sequentially controlled asynchronous sets or resets, which will destroy data. As a result, certain pattern combinations can't be scanned in, and the coverage drops dramatically.

It is best to avoid this design style, but in cases when it is absolutely necessary, the synchronous set or reset can be disabled in the test mode as shown in Figure 5. During testing, Test Enable is always high to ensure that the CLR input to D flip-flop 2 is inactive.

Note that the fault at the Q input of D flip-flop 1 isn't testable, because Test Enable is always high during testing. Therefore it is better to change the Test Enable signal to a Capture signal, so that the fault at the Q output of D flip-flop 1 is propagated through D flip-flop 2. However, this solution requires the addition of an external pin.

Bus contention Bus contention occurs when two drivers are driving different values on the same bus. Since bus contention causes severe damage to the chip, it is important to prevent bus conflicts during normal operation as well as during scan.

Figure 5. Adding a gate allows an asynchronous reset to be disabled during testing but can mask other faults in the reset circuitry.

In most designs, a bus has more than one driver. To avoid bus contention in normal operation, designers must make sure only one tristate gate at a time is selected. To satisfy testability rules, designers must set the signals for the bus drivers so that contention is eliminated in the test phase. The combinational logic signals have to be connected through an AND gate with a Scan Enable signal and added to the decoding logic (see Figure 6). In normal operation, the control signals pass through the gate unchanged, but in the test mode, the drivers are disabled so no bus contention can occur.

Figure 6. The AND gates keep the bus drivers from being activated by the normal logic during testing.

As noted earlier, several test design automation tools can help designers improve testability. Used before scan synthesis, testability analysis can help designers determine if there are any test rule violations and pinpoint where the violations are located. Testability analysis tools can quickly analyze a design; identify violations; and report the corresponding object, net, or node that must be corrected before testing begins. Tools also are available to repair the problems automatically.

Acknowledgment The authors wish to thank Samy Makar, DFT engineer at Cirrus Logic Inc. (Fremont, Calif.), for his contributions to this article.

Benson Cheung is director of applications and consulting engineering at SynTest Technologies Inc. (Sunnyvale, Calif.).

L. T. Wang is the president and founder of SynTest.

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integrated system design  August 1997