Deep-Submicron Special Section

IC Fabs: What Does It Take to Be on the Leading Edge?

A look at the issues defining deep-submicron wafer processing.

by R. T. "Tets" Maniwa

Gordon Moore of Intel articulated the now universally accepted dynamic of the electronics business known as Moore's law--the number of devices on a chip doubles every 18 months (two years, in the original version). An unofficial corollary of the law is that the cost of making the chips drops by 50 percent.

Several improvements to the IC manufacturing process are required to double the device count while halving the cost of chip manufacturing. Foremost is the need to continue pushing the limits of optical lithography. A second is to increase wafer size from the current size of 150 to 200 mm in diameter to 300 mm. In addition, for future technologies, equipment vendors must further their existing involvement in developing the IC process flow.

Pushing the limits of optical lithography One obvious way to increase the device count is to decrease the feature size. We're already seeing production at 0.35 µm, at one time believed to be below the limits of optical lithography, and we're hearing about processes with feature sizes below 0.13 µm. The latest processes, with 0.25-µm features, can achieve up to 40,000 gates per square millimeter, compared with fewer than 10,000 gates/mm ² for a 0.35-µm process.

However, although the photolithography processes may be extended one or two more generations of wafer process by moving to deep-ultraviolet light sources, eventually even the very short light wavelengths will be too large for the process features.

Another way to increase the device count is to increase the die size. The largest image size for a stepper reticule is about 25 mm on a side. Future processes will make possible even larger dice, with 35-mm die sizes projected to appear shortly after the turn of the century.

However, as die dimensions increase beyond 25 mm on a side, the number of available sites drops to well below 100 per wafer. The very large dice simply take up too much area on the existing wafers and leave too large a percentage of blank edge area on the current, 150- and 200-mm-diameter wafers. This reality is driving the trend toward 300-mm wafers.

In addition, the combination of decreased feature size and increased die size will require vastly improved optical systems, with greater resolution and precision than the Hubble telescope (after the repairs).

As the wafer-processing equipment industry creates more complex machines that work at smaller feature sizes, the cost of the machines is climbing. A current cutting-edge microlithography machine that can "map" out chips with an incredibly small feature size of 0.25 µm costs about $10 million, and a new manufacturing facility runs upwards of $1 billion.

To recapture the high cost of establishing a fab, semiconductor manufacturers demand equipment that can work on more chips at once, work faster, or do more tasks (see "Why functionality now drives equipment demand"). In other words, not only must the machines that manufacture ICs work at smaller dimensions, but because of their soaring cost, they also must process wafers faster and more efficiently.

As a result, wafer-processing equipment is changing from linear sequences of processing equipment to clusters of machines with complementary functions so that more of the 300-plus processing steps can be done in a single sequence, minimizing the manual handling of wafer cartridges (see Figure 1). Indeed, a major reason for the efforts to retain optical lithography through smaller wavelengths is the relatively high throughput of a reticule and stepper over X-ray and e-beam machines.

Economics also plays a part in the continual advance of process technology. For example, the increase in die size is driving the increase in wafer size, since larger dice mean fewer chips for a given wafer size.

Figure 1. A typical cluster alignment of processing tools arranges processing steps to minimize handling and contamination from airborne impurities while placing complementary tools in close proximity. Picture courtesy of Novellus Systems Inc. (San Jose).

The move from 150- to 200-mm wafers, which is still taking place, produces an encouraging result: The effective yields increase by more than the 16/9 increase in area. What's more, the move to 300-mm wafers is expected to follow the same trend and achieve higher yields than the 9/4 increase in area, thanks to tighter tolerances and better control of the processes. Furthermore, given a fairly fixed wafer throughput per hour, increasing the wafer size not only increases the number of dice per wafer, but also processing throughput.

Barriers to larger wafers The move to 300-mm wafer manufacturing presents several technical barriers, but those can be overcome with an investment of time and resources. The larger hurdles equipment makers face are the size of the investment required; the long-term nature of the transition (four to five years), ensuring that it will be some time before the volume production of the tools allows them to recover their investment; and the short-term pressures of doing business in the United States.

In addition, the migration to 300-mm wafers will be more difficult than planned because no single company is taking the lead. For the 200-mm wafer generation, IBM forced the technology into the market. Only Intel, with its ability to fully utilize one 300-mm fab to produce its Pentium processors can justify the cost of switching to the larger wafer size.

Thus the earliest that companies will start using 300-mm wafers will be in the 1998-2000 time frame. In the current environment, though, as soon as one IC fab begins production with 300-mm wafers, the demand for 300-mm-compatible equipment will explode as competitors scramble to match the first company's production efficiencies. Those companies that aren't positioned to offer 300-mm equipment will be relegated to being niche producers or will eventually cease to exist altogether.

Getting into the flow Equipment manufacturers also are being forced to move further into developing the process flow. In particular, they must now help to integrate the processes and the know-how for the process. There are two reasons for their taking on that responsibility.

First, because of the costs involved, semiconductor manufacturers won't put questionable technology into their new fabs, says Thomas Bowman, vice president of marketing at Novellus Systems Inc. (San Jose). Instead, they'll delay a process change or use a different process. Therefore the equipment manufacturers are taking on more of the task of process flow development to ensure the reliability of a new process.

IC fabrication: a basic view

The basic series of steps for IC fabrication starts with growing crystalline silicon (1), sawing the resultant boule (ingot) into wafers (2), and then polishing the wafers (3). Then, each wafer undergoes a series of masking steps. First, the wafers are placed in a furnace to "grow" a layer of silicon dioxide (oxide) (4). Next, a liquid photoresist (resist) is spun onto the wafer (5). Then, the wafer is exposed to ultraviolet light passed through a mask (6) and processed to leave the mask pattern (7). Etching removes the exposed oxide (8), and dopant ions are introduced into the exposed areas of silicon (9-10). The remaining resist is then stripped away (11), as is the unwanted oxide (12). Steps similar to 4-12 are repeated for each layer­typically 12 to 20 times for a CMOS process. Source: J. M. S. Smith, Application Specific Integrated Circuits

Second, the new processes are going to be much more complex than current production processes (see "IC fabrication: A basic view"). The number of process steps is expected to soar from some 300 for 0.35-µm technology to over 1,000 for the 0.13-µm generation. Furthermore, the starting material may be silicon on insulator rather than the current bulk silicon. Handling such complexity requires that process development move from the fab processing engineers to the equipment vendors.

As a result, equipment vendors are working to develop the process technologies for the next two or three generations of wafer fabrication. However, this change in roles affects the development process for their equipment: Since process generations are about one and a half to two years, the manufacturers have to develop today's machines so that they are capable of processing tomorrow's products and can be used to develop the day after tomorrow's processing.

Novellus's Bowman adds that manufacturers see the need to evaluate a process while developing the equipment for that process. The initial concerns are wafer yield and reproducibility.

The expectation is that the demand for greater circuit density and higher-performance ICs will continue to drive the processing equipment manufacturers and the industries that make the ancillary processing products to ensure that Moore's law will hold at least through the next 10 years. *

Acknowledgement The figure illustrating IC fabrication is from M.J.S. Smith, Application Specific Integrated Circuits (Fig. 2.6). © 1997 Addison Wesley Longman Inc. Reprinted by permission of Addison Wesley Longman Inc.

R.T. "Tets" Maniwa is the technical editor at Integrated System Design.

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integrated system design  September 1997