Design Automation

Deep-Submicron Designs Require Netlist Reduction for Fast Simulation

Hitachi uses a new tool to reduce cache memory megacell netlists to a manageable size.

by Jack S. Thomas, Amod Kale, and You-Pang Wei

Characterizing microprocessor cache memory megacells is a challenging process. It involves the combination of very large arrays with complex control logic with the need to provide accurate timing. Dynamic simulation is necessary, but getting a netlist with the required parasitic elements for accurate simulation is fraught with difficulty. It often becomes a manual cut-and-paste process that is difficult to repeat. In addition, associative cache memory megacells often contain clock delay cells and pulse generators that provide precise timing for the sense amplifier and comparator circuits. These delayed and specially shaped signals also time the control logic; available static timing tools that extract circuit netlists based on critical path identification, however, don't model these types of circuits well. Therefore the arrays and the control logic pins call for different reduction methods.

A new program that extracts a netlist containing only the relevant sections of the memory array from a very large RC distributed netlist can reduce simulation size and time while preserving accuracy, so that we can perform the simulation with Hspice, from Avanti Corp. (Fremont, Calif.). The program traces and identifies only the circuit elements that are activated by the imposed external address and control pin waveforms. The memory cells that aren't in the active path are instead accurately represented only by their loading effects. The reduced netlists are placed in separate files in a ready-to-simulate form and are easily translated into timing models from simulations results. For three-dimensional circuit layout extraction netlists, we've been able to achieve fast and accurate reductions in the range of 97 percent.

Characterization flow The complete flow is shown in Figure 1. We extract a netlist of a complete megacell with Arcadia, an RC extraction tool from Synopsys Inc. (Mountain View, Calif.). Then we reduce the RC portion of the netlist with RC-Cut, a program from from Legend Design Technology Inc. (Los Altos, Calif.) based on asymptotic waveform evaluation (AWE), to obtain the master netlist. The next step is the most crucial and is the key to the characterization process. Megacell pins are categorized based on whether there is a latch or flip-flop between the pin and the memory array. If the pin connects directly to the memory array or to a holding latch, then the waveform activation method must be used to reduce the netlist; otherwise, subcircuit pattern matching may be used.

We extract one complete netlist for each pin of the megacell using Legend Design's SpiceCut. For input pins, the extraction stops at the outputs of sequential elements. All circuitry that is dependent on an input pin is cut out of the megacell netlist and included in a separate netlist for that pin. In addition, Hspice control statements are automatically generated for an input pin and its related clocks to perform a bisection (a binary search method used in Hspice to find an unknown target value) and directly measure the setup and hold times. The control statements include a group of input slopes to provide a 1 x n lookup table.

The same process is performed for the output pins, except that the circuit tracing is backward and stops when all dependencies are found. A slightly different process is performed for purely combinatorial pins. In that case, control statements are generated for an n x n lookup table accounting for both slope and load.

The pin netlists must be hand-checked and adjusted based on insights into the megacell design, but most of the pins can be simulated and measured without adjustment. Thus the designer can focus on the more difficult pin characterizations.

Figure 1. For accuracy and performance, the characterization process should include layout extraction, RC reduction, circuit reduction, and circuit simulation.

The completeness of the data and the efficiency of the method facilitate the process of adjustment at each phase. For example, Arcadia can rewrite the netlist for our cache memory example from its database in about 5 minutes. SpiceCut, given a change in its control file (such as finding a different latch structure), can write a pin netlist in about 10 minutes. This process offers a tremendous advantage over traditional reduction flow methods, such as layout masking.

We use Arcadia to extract a netlist from layout in our megacell characterization. It takes about an hour to create a technology file, and we can obtain detailed Hspice netlists within the first day. Running Dracula LVS, from Cadence Design Systems Inc. (San Jose), before the extraction provides complete correlation between schematic node names and layout netlist names. However, long names in the flat netlist caused by the hierarchy must be shortened because of limits in the string length for Hspice. The shortening and cross-referencing are deferred to the final stage of SpiceCut to facilitate debugging.

RC reduction with RC-Cut For accurate results, both resistance and capacitance should be extracted from the layout. After initial extraction, the size of the Hspice netlist is very large, and the number of resistors and capacitors must be reduced for efficient characterization. Too many resistors and capacitors slow down circuit simulation dramatically because of the non-linear effect of node count on run time.

As noted, we use RC-Cut for the reduction. In RC-Cut, the entire circuit is partitioned into segments based on DC connectivity. Then each segment of RC is transformed into a smaller one by using an extension of the AWE technique. The effects of coupling capacitances between segments is always preserved without decoupling them in the reduction process.

The degree of reduction can be controlled by specifying two independent parameters: error tolerance and signal frequency. The ability to control reduction by specifying error tolerance is important because simple thresholding of the resistance and capacitance can introduce unacceptable errors into lower-capacitance nets.

Reduction results in our example were 77 percent for the memory layout, with a 5 percent error tolerance and port merging allowed (see Table 1). The reduction percentage refers to the ratio of eliminated RC elements to the number before reduction.

One might expect greater reductions, but the results depend greatly on the type of circuit being reduced. Logic circuits reduce much better than memory and datapath circuits--we've achieved reductions as high as 99 percent. The reason is that logic circuits are characterized by longer wires, more wire corners, and more contacts, due to level changes. However, most suppliers of reduction tools don't publicize that fact.

Pattern activation reduction In our cache memory case, the SRAM array of 1,024 x 16 bits has about 100,000 transistors. In addition, the number of parasitic elements is 450,000. Running a simulation therefore requires that the memory array extracted from the layout be modeled by just the active parts of the circuit and their equivalent loading. SpiceCut has proved to be an effective automatic way of generating that small memory array model (see Figure 2).

Figure 2. The waveform activation reduction automates the process of memory circuit reduction by using the input address and control waveforms. The netlist shown in gray is extracted for this circuit path.

We extracted the simulation netlist from the master netlist using the following procedure:

• Define the pattern of the memory cell as a .SUBCKT in Spice format. The type of memory cells used may be single- or dual-port. Transistor sizes may also be used for discriminating between memory cell types.

• Construct the structure of memory banks after recognizing all memory cells in the circuit.

• Recognize active memory word lines by analyzing the logic patterns of address pins and relevant control pins.

• Recognize active memory bit lines by analyzing data-in/data-out pins and the logic states of address and relevant control pins.

• Model the active bit lines by the number of segments specified by a command. For example, if each segment is specified to have 64 word line loads (MOSFETs) at most, each segment is represented by a pi-shaped RC network and a MOSFET with a multiplier of 64.

  Table 2
  Memory circuit reduction performance
  	Transistors	Rs	Cs
  Before SpiceCut	92,028	556,846	419,809
  After SpiceCut	2,973	25,352	22,057
  Reduction	97%	95%	95%

• Initialize memory cells with the default states or by control file specifications (or a combination of the two). The initialization is extremely critical for the circuit simulation to converge.

• Generate a final reduced netlist by excluding the nonrelevant parts of circuits. After adding the input waveforms and control statements, the netlist is ready for running circuit simulation.

For the cache memory design, we selected two active word lines and 44 bit lines in one bank. In this case, we achieved reductions of 95 to 97 percent (see Table 2).

Latched megacell pins Modeling standard cell timing for submicron designs has necessitated the use of non-linear lookup tables in order to represent the effects of input signal transition time. Each output pin must be simulated with different slopes on each of its related input pins. In addition, these combinations must be run with different output pin loads. This results in a two-dimensional lookup table for each output pin and requires many simulation runs to characterize.

The problem with megacells is that they have circuit netlists that are too large to take advantage of the cell-modeling methods developed by the industry for standard cells. For that reason, all characterization environments must compromise by using a less accurate netlist, a less accurate simulation, or both.

Most megacell pins require only one-dimensional tables, because the inputs and outputs are isolated from each other by gating and buffering before terminating on the latch. However, to fill in the one-dimensional tables, each pin still requires several runs, and usually there are combinational paths that require the full two-dimensional tables.

Since interface timing is the reason for modeling the megacell pins, all that's needed for each pin is a netlist containing only the paths affecting its timing. These paths terminate on clocked elements and other pins. SpiceCut traces these paths inside the master netlist and eliminates tiny netlists with three to four orders of magnitude fewer components with no loss of accuracy. The simulation accuracy is maintained by having active circuit elements, dynamic loading devices, and parasitic RCs exactly the same as the master netlist.

In addition, the pin netlist that is written out is prepared for simulation with Hspice control statements. These control statements set up Hspice to perform a bisection search to measure setup times for pins terminating on latches. Hspice also measures clock delay to the latch pins and output delay for output pins.

The setup for these measurements is accomplished with a flexible control file that allows the specification of the values that appear in the netlist header and trailer. Any number of input transition times and output loading capacitances can be specified to initiate measurement of the values needed for the one-dimensional tables. In the case of combinational pin-to-pin timing arcs, both parameters can be specified and the netlist will automatically be written with all the necessary combinations in ALTER statements.

By default, all related pins are tied low to a voltage source in the netlist header. The user must specify the pins that must be tied high in order to enable the critical path, or need PWL (piecewise linear) waveforms.

SpiceCut writes out the pin netlists very fast. For the megacell discussed, it wrote 1.51 to 3.5 pin netlists per minute.

For performance, SpiceCut first compiles a megacell-cell Hspice netlist to an integrated database. Then multiple netlist reduction and extraction jobs can be performed very fast with efficient access to the circuit database. We use a mixture of backward, forward, depth-first, and breadth-first searches for efficiency.

For full automation and maximum efficiency, SpiceCut has adopted:

• partition schemes for removing the irrelevant parts of circuits and preserve dynamic loading

• pattern recognition schemes for identifying latches, flip-flops, and pins where the user specifies the subcircuit transistor netlist of the clocked subcircuit to be recognized

• input waveform generation with slope variations

• output loading with capacitance variations

• automated initialization of latches in the netlist to facilitate simulation

• measurement and output statement generation

• bisection modeling for an accurate setup time through an optimization process

• pin capacitance measurement accounting for transistor gate, source/drain area and perimeter, and wire capacitance

In preparing a circuit database, SpiceCut incorporates the technology parameters from Hspice models for capacitance calculation. For example, the gate oxide thickness (tox) is used to calculate unit gate capacitance, and shrink factor and effective channel length and width are used to determine gate area. The total pin capacitance obtained from a SpiceCut database includes diffusion capacitance (AD, PD, AS, PS, and diodes), MOSFET gate capacitance, interconnect capacitance, and MOSFET Miller capacitance.

Library translation Library translation is the easiest step and includes the extraction of measurement results from HSPICE runs. It also includes reasonableness and consistency checks, verification of port names between circuit netlists, Verilog netlist templates, and layout pin text.

In addition to approximately 100,000 transistors, the megacell contains 32,000 nets and 178 pins. Table 3 gives the run time and file sizes for the cache memory characterization. All times are expressed in UltraSparc CPU time. *

Jack S. Thomas is a manager at Hitachi Micro Systems Inc. (San Jose).

Amod Kale is a staff engineer at Hitachi Micro Systems.

You-Pang Wei is a manager at Legend Design Technology Inc. (Los Altos, Calif.).

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integrated system design  November 1997