TOOLS AND TECHNOLOGIES

Products and services for system design

Simulators Model Technology introduced V-System/VLOG PC, a Verilog simulator, and V-System/PLUS PC, a single-kernel simulator for mixed-HDL designs. V-System/VLOG PC offers a gate- and RT-level simulator, which incorporates the capabilities of Model Technology 's V-System simulators, including full language support, protection of intellectual property cores independent of language, interactive debugger, and direct compile architecture for machine independence. V-System/PLUS PC enables direct access to the capabilities and libraries of applications using both Verilog and VHDL. V-System/VLOG PC is priced at $5,995. V-System/PLUS PC, with both Verilog and VHDL licenses, is priced at $8,995. V-System/VHDL PC is upgraded to V-System/PLUS by purchasing V-System/Verilog. All existing V-System/VHDL PC customers on maintenance will get free 30-day VLOG evaluation kits. V-System simulators run on Windows 3.11, 95, and NT 3.5. Model Technology Inc., Beaverton, OR. Contact (503) 641-1340, sales@model.com, or www.model.com.

RISC microprocessor The IC Division of Toshiba America Electronic Components announced its new RISC microprocessor, the TMPR3903F. The application-specific standard product (ASSP) is designed to meet the needs of the market that develops vehicle navigation and driver information systems. Making use of the R3900 RISC core, based on MIPS R3000A CPU, the R3903F ASSP incorporates the on-chip functionality necessary to drive a color LCD monitor, four universal asynchronous receiver and transmitter (UART) channels, 16-bit parallel I/O, and two DMA channels that are suitable for connection to memory, sensing, and control devices. The R3903F provides a graphics controller, color palette, and a three-channel, 16-bit, D/A controller for output of red, blue, green (RBG) data to a 320 by 240 resolution LCD display (other LCD resolutions are also possible). Samples and full production quantities for the TMPR3903F are available now. Pricing in 10,000 piece lots is $15. The device comes in a 208-pin PQFP. Toshiba America Electronic Components Inc., IC Division, San Jose, CA. Contact (800) 879-4963 or www.toshiba.com.

0.35-µm standard cell library ASIC Semiconductor is now offering its 0.35-µm standard cell library for applications in computing, graphics, and communications. Called the FS8000, the library offers 78-ps gate delays and a power rating of 0.48-µW/gate/MHz at 3.3 V. The library is available in single-poly, three- and four-layer metal, with over 470 core macrocells and 330 I/O functions. The library is optimized for any of UMC's fabs. Pricing starts at $60,000. ASIC Semiconductor International Corp., Santa Clara, CA. Contact (408) 235-8888 or www.asicasic.com.

EDA system for PCs MicroSim announced MicroSim DesignLab, an EDA system for Windows that has a single user interface for designing mixed analog/digital circuits from start to finish. MicroSim DesignLab enables engineers to see all facets of their design in a single system, including schematics, analog and digital simulation, PLD and FPGA, and printed circuit board layout. Engineers can move throughout each phase of the design cycle and make changes that flow through all of the documentation. MicroSim DesignLab is available immediately with pricing starting at $13,500. MicroSim Corp., Irvine, CA. Contact (714) 770-3022, sales@MicroSim.com, or www.microsim.com.

No NRE gate arrays Chip Express introduced the "Gate Array Express" program offering no NRE and a few iterations with a minimum production order of only 900 devices. To accelerate time to market, the offering of a few free iterations is expected to encourage designers to adopt the interactive approach of multiple design re-spins. Early and frequent prototyping is associated with faster development and higher rates of problem detection. Chip Express Corp., Santa Clara, CA. Contact (408) 235-7300 or www.chipexpress.com.

PLI and SDF Wellspring Solutions announced VeriWell 2.1. The new version of VeriWell includes a full programming language interface (PLI) option and a standard delay format (SDF) option. VeriWell's PLI support includes almost all of the "tf" and "acc" routines specified in the IEEE-1364 standard. Existing code written for other simulators will run with little or no modification. SDF allows delays to be backannotated into a Verilog model. PLI is immediately available for Windows 95, Windows NT, Macintosh, Sparc, and Linux and is priced at $895. SDF for VeriWell is also immediately available and is priced at $495. Wellspring Solutions Inc., Sutton, MA. Contact (508) 865-7271, info@wellspring.com, or www.wellspring.com.

DSP for wireless Texas Instruments announced a single-chip digital signal processing (DSP) solution that integrates all the digital baseband functions necessary for the design of digital wireless telephones. The standard-independent digital baseband platform is optimized for phones, pagers, and other types of wireless systems. The main functions are in a TMS320C454x DSP core and a thumb core licensed from Advanced RISC Machines Ltd. The digital platform is supported by TI's 0.25-µm TSC5000 CMOS standard cell library for additional functions that can operate below 2.0V. The cores and standard cells are available immediately. Pricing depends upon customer design configuration. Texas Instruments Inc., Semiconductor Group, Dallas, TX. Contact (800) 477-8924 x4500 or www.ti.com.

Virtual system IC prototypes CAE Plus announced the release of ArchGen version 1.4. ArchGen is used to create clock-edge accurate virtual prototypes of system ICs, which can be used to validate hardware/software functionality prior to hardware implementation. Clock-edge accurate specifications are captured as data/control graphs for specification validation early in the design process. Outputs are synthesis-ready RTL. Pricing starts at $60,000 for ArchGen 1.4, plus $10,000 each for output translators for Verilog, VHDL, or C. CAE Plus Inc. Austin, TX. Contact (512) 338-0165, comm@cae-plus.com, or www.cae-plus.com.

Foundry IMP announced two new wafer foundry processes for analog mixed-signal applications. The 100-V capable C1024 CMOS process is designed for power control, electroluminescent and flat panel display electronics, and microcontroller interfaces. The C1219 process features EEPROM technology and low threshold voltages for battery operated systems. Access to IMP's mixed-signal foundry can take many paths. IMP has a wafer fabrication and manufacturing services handbook describing the many available processes and programs. IMP Inc., San Jose, CA. Contact Roger Meade at (408) 434-1228, e-mail info@impinc.com, or www.impweb.com.

System design tools Synario Design Automation announced a system and board design environment. Synario System Design Solution takes the functions in Synario Programmable IC Design Solution and adds printed circuit board layout capabilities. The System Design Solution allows designers to continue using their current methods, but also take advantage of top-down techniques. The new modular tools provide built-in expert-user knowledge for the targeted design application. Features include a project navigator, a hierarchy navigator, parts library, PCB layout interfaces to industry standard tools, and forward-annotation and back-annotation. Individual modules are priced between $1,500 and $5,000. The tools are available immediately. Synario Design Automation, Redmond, WA. Contact (206) 881-6444, edasales@data-io.com, or www.synario.com.

Interactive Boolean simulation SynaptiCAD has announced an upgrade to its WaveFormer Pro. WaveFormer Pro v3.0 is a CAD tool that supports interactive Boolean simulation. With WaveFormer, designers can enter Boolean equations that describe their design and immediately assess the impact of modifying logic, state, and timing information without having to change a schematic or create simulation models. The Boolean simulator includes support for propagation and interconnect delays, allowing any combinatorial logic to be modeled. This feature combined with its timing analysis features allow users to ask and answer "what-if" questions before they have even created a schematic. Other features added in v3.0 include weak high/weak low states for VHDL and Verilog stimulus generation, new image formats (Windows Metafiles, FrameMaker MIF, and previewable EPS), sampling parameters, time markers, and import/export support for more waveform formats, including Mentor's QuickSim II simulator. WaveFormer Pro v3.0 is currently available on Windows 3.1, 95, and NT for $975, and it is available on Solaris, SunOS, & HP-UX for $2000 (floating license). SynaptiCAD Inc., Blacksburg, VA. Contact (800) 804-7073, (540)953-3390, sales@syncad.com, or www.syncad.com/.

To voice an opinion on this or any Integrated System Design article, please e-mail your message to michael@isdmag.com.

integrated system design  January 1997