TOOLS AND TECHNOLOGIES

Products and services for system design

ATM design environment The Alta Group of Cadence Design Systems Inc. announced the BONeS Asynchronous Transfer Mode Verification Environment (BONeS ATM VE), a verification environment created specifically for efficient design of ATM-compliant products. The BONeS ATM VE provides support for System architecture, protocol modeling, and performance evaluation. Key capabilities include system building blocks, multi-layer protocol modeling, performance analysis tools, and application-specific support. Available now, the BONeS ATM VE is priced at $25,000. Prerequisites include BONeS Designer, priced at $18,000, and Finite State Machine Editor, priced at $6,000. Alta Group, Sunnyvale, CA. Contact (408) 733-1595.

RF simulator Avista Design Systems announced a new release of Spectre/XL for RF & Microwave Design, version 1-B2. The tool provides interactive simulation of non-linear communications circuits--such as mixers, receivers, and oscillators--as well as frequency translation of signals and noise. Spectre/XL simulates noise voltage at any node in the circuit, similar to the RF power spectrum measured by a spectrum analyzer. Spectre/XL uses standard Spice and Libra models for non-linear devices, such as diodes and transistors, for compatibility with vendor libraries. Linear devices, such as microstrip devices, use industry-standard models and formulas. Free demonstration software of Spectre/XL for RF and Microwave Design is available at Avista Design's Web site at www.avista.com or upon request. It is $2,250, including shipping, and is available immediately. Spectre/XL requires either Excel 97, Excel 7.0, or Excel 5.0 for Windows from Microsoft Corp. (Redmond, WA). Avista Design Systems, Folsom, CA. Contact (916) 985-6080, (800) 985-6080, avista@avista.com, or www.avista.com.

Cable receiver VLSI Technology announced the VES1520, a single-chip, digital video broadcasting (DVB)-compliant, wide-range digital cable receiver IC. The device combines continuous variable-rate QAM demodulation supporting symbol rates between 0.87 and 8.7 Mbaud, forward error correction (FEC) functions, an adaptive equalizer for echo cancellation, digital anti-aliasing filters, and on-chip digital clock generation. The VES1520 interfaces directly to a 9-bit A/D converter and provides it with a fixed frequency clock. The chip has a carrier acquisition range of up to 8 percent. It outputs fully QAM demodulated, deinterleaved, and Reed-Solomon decoded data for use by an MPEG-2 transport demultiplexer. The VES1520 is offered in a 100-pin MQFP package. Samples will be available beginning in January of 1997 with production quantities expected in the Q2 of 1997. It is priced at $20.00 in 10,000 unit quantities. International pricing may vary. VLSI Technology Inc., San Jose, CA. Contact www.vlsi.com.

Digital audio processor Zoran announced an advanced AC-3/MPEG2 digital audio IC that uses 75 percent of its available processing power for audio decoding, thereby making 25 percent of the chip's processing resources available to audio/video system manufacturers for product differentiation. With the programmable ZR38600, system manufacturers can provide customized product features while simultaneously decoding multi-channel audio. In addition, the ZR38600 implements several DVD-ready functions on-chip, and it integrates system functions into a single chip in order to optimize performance and reduce system cost. The ZR38600 is available immediately in sample quantities with volume production scheduled for the Q1 of 1997. The ZR38600 is priced at under $20.00 in high volume. The ZR38600 demonstration board is priced at $895. Zoran Corp., Santa Clara, CA. Contact (408) 986-1314.

Embedded controllers AMI introduced the 3XX family of masked programmable system devices (MPSDs). MPSDs are field programmable devices used to address the embedded-controller MPSDs and include ROM, RAM, and logic functions on a single device. The initial 3XX offering includes three separate devices: MPSD3X1 (256k), MPSD3X2 (512k), and the MPSD3X3 (1 Mbit). Samples of the MPSDs are available immediately with volume production beginning in December of 1996. Prices are for quantities of 10,000 and range from $5.00 for the MPSD3X1, $5.50 for the MPSD3X2, and $6.00 for the MPSD3X3. AMI, Pocatello, ID. Contact (208) 233-4690 or www.amis.com.

Mixed-signal semiconductor testers Hewlett-Packard Co. announced a new family of mixed-signal semiconductor testers, the HP 94000 Series. The new family provides a test solution for mixed-signal, multimedia, and other broadband communications devices. The HP 94000 Series is also suited for testing commercial devices, such as A/D and D/A converters, baseband communications devices, and other established mixed-signal chips. The HP 94000 Series is completely compatible with the current HP 9490 Series of mixed-signal testers. The existing device-under-test (DUT) boards and test-program software do not have to be altered to run on the new HP 94000 Series. Pricing for the HP 94000 Series starts at $600,000. First shipment is expected in early spring. Hewlett-Packard Co., Test and Measurement Organization, Palo Alto, CA. Contact (800) 452-4844 x5031.

Memory test system The Memory Test Division of Teradyne introduced its new J996 Memory Test System. The J996 is a high-performance test system for engineering characterization and volume packaged-device test of RAMs operating at speeds up to 250 MHz, including standard DRAMs, synchronous DRAMs, and synchronous SRAMs. The J996 uses Teradyne's IG900+ software system, and it is fully compatible with other J990 Series memory test systems. IG900+, which is also used in Teradyne's VLSI test systems, provides a full suite of graphical engineering software tools and templates optimized for production testing. Parallel testing is integrated into the IG900+ executive software, which provides efficient program development and control of test flow and binning. Typical pricing for the J996 system is under $2 million for volume purchases. Shipments of J996 systems are scheduled to begin in Q1 of 1997 to customers in the U.S., Europe, and Asia. Teradyne, Agoura Hills, CA. Contact (818) 991-2900.

Interconnect analysis products Ultima Interconnect Technology introduced its first interconnect analysis products: Ultima-PR and Ultima-DC. Ultima-PR reduces extracted parasitic data to decrease the computational and storage burden of IC simulators. Ultima-DC computes cell and interconnect delays for deep submicron IC designs. For each pair of input and output pins, Ultima-DC accurately computes effective capacitance for different input rise times by matching the driving point waveform. Unix versions of Ultima-DC and Ultima-PR running on Sun and HP workstations are shipping now. Unix versions for DEC and IBM workstations will ship in Q1 of 1997. Prices for Ultima's products start at $35,000. Ultima Interconnect Technology Inc., Cupertino, CA. Contact (408) 725-0738, info@ultimatech.com, or www.ultimatech.com.

MIPS RISC model CAE Plus announced a MIPS RISC model that can be customized for new instructions and architecture to yield a clock-edge accurate instruction simulator for a specific architecture and instruction set. The clock-edge accurate C model executes instructions at 15,000 cycles per second on a Pentium 133-MHz machine. The CAE Plus MIPS model consists of a five-stage pipeline, including register forwarding and register file with 32 entries, and it has interrupt capabilities. It accurately models concurrent stalls resulting from load dependencies, instruction and data cache misses, and multi-cycle instructions such as multiply, multiply-accumulate, and divide. The MIPS model reads the object file produced by assemblers or C compilers and executes the instructions from instruction memory, emulating the real program execution. CAE Plus Inc., Austin, TX. Contact (512) 338-0165 or www.cae-plus.com.

Library migration tool Cascade Design Automation announced MasterPort 2.0, an IC library migration tool that produces process-optimized libraries of complex, hierarchical elements, such as memories and datapaths. It allows IC library developers to migrate existing cell libraries from one process technology to another. New features, such as automatic jog insertion and automatic cell height calculation, allow library developers to achieve more quickly their desired results. The jog insertion feature allows the user to control the extent of its usage with respect to critical paths, user-selected paths, and gates. The automatic cell-height calculation feature determines and applies the minimum cell height for an entire standard cell library. MasterPort 2.0 runs on workstations from Hewlett-Packard and Sun Microsystems and is available immediately. The stand-alone MasterPort 2.0 price is $180,000. The price for MasterPort 2.0 with the hierarchy migration capability option is priced at $250,000. Cascade Design Automation, Bellevue, WA. Contact (206) 643-0200.

Mask ROM Sharp Electronics Corp. (Camas, WA) announced the LHMD79XX and LHMD59XX mask read only memories (MROMs). These new MROMs are designed for 32-bit embedded systems. The MROMs feature 1-Mbit depth by 32-bits, or 2-Mbit depth for use in 16-bit systems. Sharp expects the 32-bit configuration to be used in many embedded system applications where it will reduce overall parts count, eliminate some system overhead, and improve system performance. Other features of the LHMD79XX and LHMD59XX include 3.3-V operation that saves power and reduces heat, 100-ns access speed, and 30-ns page mode access for measurably improved operating speeds. The LHMD79XX is currently sampling in a 70-pin SSOP. Samples are available now with production quantities shipping in the Q2 of 1997. Sharp Electronics, Camas, WA. Contact (800) 642-0261 or www.sharpmeg.com/.

integrated system design  February 1997