TOOLS AND TECHNOLOGIES

Products and services for system design

BIST tool LogicVision introduced icBIST, the sequel to their IC BIST technology. icBIST features a new architecture to support high-speed designs, enhanced automation tools, and memory BIST technology that allows testing of embedded DRAM, SRAM, and ROM. It provides at-speed testing of high-speed logic (50 MHz or greater), which eliminates the "test escapes" often associated with running BIST testing below an IC's normal operating frequency. Its automation technology configures the BIST design objects (controllers) for the target design, and it automates the process of embedding the objects into the design and stitching them together. icBIST also includes the new memory BIST technology, memBIST-IC, an automated solution for testing all embedded memory types via a single, small controller (1,000 gates). icBIST is licensed on a per-design basis, with fees starting at $46,500 per design for the first three designs. The memBIST-IC is also available separately. License fees start at $16,700 per design for the first three designs. LogicVision Inc., San Jose, CA. Contact (408) 453-0146, info@lvision.com, or www.lvision.com.

Synthesis tool Cadence Design System Inc.'s Alta Group introduced Visual Architect (VA), an application-specific behavioral synthesis tool designed to be the architectural-entry point of a system-to-silicon design flow for implementing ASICs and FPGAs. VA was designed to close the gap between the system-level algorithm expert and the HDL-based ASIC expert. The Alta Group claims VA provides full control architectural decisions within the context of the user's application and that its graphical user interface (GUI) enables system designers to evaluate synthesis results without requiring an intimate knowledge of HDLs. VA can be integrated into Cadence's logical, physical, and datapath design solutions, or it can be interfaced to other commercial or proprietary tools. VA is available now on Sun and HP Unix machines for $70,000. Alta Group of Cadence Design Systems Inc., Sunnyvale, CA. Contact Melissa Baten Caswell (800) 859-9805 or www.altagroup.com.

PCB design system Zuken-Redac announced CADSTAR for Windows 2.2, the latest evolution of its 32-bit PC/Windows-based PCB design system. The new range of capabilities found in this release address both the demands of advanced board design and the requirements for engineering productivity improvements for individuals and workgroups. New CADSTAR tools include the Report Generator, a graphical programming interface for producing customized reports, outputs, and assembly machine drive files for manufacturing, based upon user requirements; Route Editor 2000 Elite, which combines Zuken-Redac's shape-based Route Editor 2000 and the Quad Field Designer from Quad Design Inc.; and CADSTAR Design Viewer, which provides affordable access and sharing of all schematic and PCB design data for workgroups. CADSTAR for Windows 2.2 has a new graphical user interface, based on the Microsoft MFC programming library. The CADSTAR Design Viewer pricing ranges from $650 for a single seat to over $6,500 for a site license. Route Editor 2000 Elite is priced from $15,000. CADSTAR for Windows 2.2 products are shipping now. Zuken-Redac, Santa Clara, CA. Contact (408) 562-0177.

RTL formal verification Chrysalis announced Design INSIGHT, a new family of formal verification and design products for validating the functionality of RTL design specifications. The Design INSIGHT family features a State Machine Analyzer module that solves RTL verification problems such as deadlock, mutual exclusivity, and unexpected transitions, and it can be used on existing synthesizable RTL models. Each Design INSIGHT module adds verification commands and new graphical visualization tools to those provided by Design Explore. The Design INSIGHT State Machine Analyzer module runs on SparcStations, HP 9000/700, IBM RS/6000 workstations and servers, and it is available now for $45,000. Chrysalis Symbolic Design Inc., Billerica, MA. Contact (508) 436-9909, www@chrysalis.com, or www.chrysalis.com.

Terminator transceiver chipset Vitesse Semiconductor introduced the VSC8023 and VSC8024, an integrated 2.5-Gbit per second section terminator transceiver chipset that allows byte interleaving and de-interleaving four 622-Mbit per second data buses into and out of a serial 2.5-Gbit per second serial data stream. The VSC8023 and VSC8024 chipset has been designed to interface directly with PMC-Sierra's UNI devices. The chipset is suited for SONET and SDH transmission systems, ATM systems, video distribution, and SONET/SDH test equipment. The features of the VSC8023 and VSC8024 include an OC48c mode, equipment and facility loop back modes as well as optional frame synchronous scrambling and descrambling functions. The devices calculate and insert a bit-interleaved parity-error code and declare receiver errors. The VSC8023 and VSC8024 are packaged in 192 TBGA packages with integrated heat spreader for optimum speed performance, thermal performance, and reduced cost. Requiring only +3.3 V and -2 V power supplies, the devices allow standard TTL levels on the low-speed interfaces and standard ECL levels on the high-speed signals. Sample quantities are available now, with volume production in March of 1997. Production pricing for each chip is $300 in 1,000 piece quantities. Vitesse Semiconductor Corp., Camarillo, CA. Contact (805) 388-3700.

Emulation system & tool integration Quickturn introduced two new products: the CoBALT (Concurrent Broadcast Array Logic Technology) Emulation System, and Q/Bridge, a software tool that integrates "best-in-class" commercial verification products with Quickturn's System Realizer or CoBALT. The architecture of the CoBALT emulation system is based on an array of concurrent custom processors. It enables designers to perform in-circuit emulation and accelerated co-simulation in either dedicated or server modes to rapidly prototype multi-million gate ICs (systems on silicon) or full systems composed of multiple ICs. Quickturn claims CoBALT has a compilation speed of 1 million logic gates per hour and that it has a logic and memory capacity accommodating up to 8 million logic gates. The CoBALT Emulation System starts at $495,000 for an entry-level 500-kgate configuration. Q/Bridge allows third-party vendors of EDA tools to easily create co-simulation interfaces between their products and Quickturn's Quest II emulation software environment. Q/Bridge allows integration of Quickturn's emulation systems with testbench generation tools, cycle-based simulators, full-timing simulators, software debug tools, and C models for interactive exchange of vector stimuli. It enables the emulator to operate as a fast, functional hardware accelerator that leverages the user's existing behavioral testbenches in co-simulation mode. The Q/Bridge Integration Kit--which includes Q/Bridge, Quickturn Emulation Language (QEL), the design API, and the vector API--is available immediately to qualified EDA partners. Q/Bridge will be available to Quickturn emulation system users starting in Q2 of 1997 for $25,000. Quickturn Design Systems Inc., Mountain View, CA. Contact (415) 967-3300, info@quickturn.com, or www.quickturn.com.

integrated system design  March 1997