TOOLS AND TECHNOLOGIES

Products and services for system design

VLSI signal integrity package Pacific Numerix announced its IC signal integrity program, VLSI Signal Integrity. This specialized electrical analysis program is capable of detecting and correcting signal integrity problems, including wave propagation delay, clock skew, waveform distortion, crosstalk noise, electromigration (metal migration), power saturation, and ground-bounce frequently seen in high-frequency and deep submicron IC designs. Two-D and 3-D parasitic models are automatically created for each structure on the IC, and frequency-dependent RLCG are extracted. Additional capabilities include power-line current and voltage distribution analysis as well as a hierarchical database. The hierarchical database allows the chip design to be flattened to any level automatically. Extremely accurate interconnect delays can be backannotated to logic simulators through an SDF interface. VLSI Signal Integrity runs on most Unix workstations. It is available now, and pricing starts at $30,000. Pacific Numerix Corp., Scottsdale, AZ. Contact (602) 483-6800, info@pnc.com, or www.crl.com/~pacnum/pnc.html.

Programmable logic synthesis Synplicity announced HDL Analyst, a synthesis add-in tool that offers visual feedback on an HDL design via RTL schematic and gate-level schematic views. This feedback provides designers with information to iterate and fix problems earlier in the design cycle. The multi-level viewer capabilities permit the user to cross probe among any of the views by selecting any HDL, RTL, or gate-level object in its respective window and seeing corresponding objects in other windows. In addition, the post-synthesis schematic view provides the user with a view of the target architecture's logic modules. The HDL Analyst works in conjunction with the new release of Synplify 3.0. Enhancements to the Synplify timing engine now enable users to specify frequency on a clock or multiple clock networks, and Synplify will optimize to that timing specification for the entire design. In addition, Synplify 3.0 includes new resource-sharing and optimization capabilities. Pricing for the HDL Analyst for a node-locked Windows platform is $4,000. Pricing for the Synplify 3.0 for a node-locked Windows platform is $12,000. Floating licenses for Unix are $8,000 and $24,000, respectively. Synplicity Inc., Mountain View, CA. Contact (415) 961-4962, info@synplicity.com, or www.synplicity.com.

Analog DFT tools Opmaxx launched its new family of tools for analog design and test automation, consisting of DesignMaxx, FaultMaxx, and TestMaxx. DesignMaxx enables designers to perform "design centering" of analog circuits in minutes by fully measuring a design's sensitivity to DC, AC, and transient circuit simulation. FaultMaxx allows design engineers to achieve analog fault coverage of their designs. It combines the results of DesignMaxx' sensitivity analysis with design layout data and schematic connectivity for complete analog fault modeling and computation. FaultMaxx uses a systematic approach that automatically partitions faults into two categories: hard faults, which are catastrophic failures; and soft (parametric) faults, which are component or process variations that cause circuit malfunctions or marginal system failures. TestMaxx is an analog test tool capable of generating a structured set of tests for DC, AC, and transient conditions, including complete detection of both hard and soft faults. TestMaxx uses information from DesignMaxx and FaultMaxx to automatically create an optimized analog test environment that delivers savings in both test development time and automatic test equipment (ATE) test time. DesignMaxx is available today for $70,000. Available in Q2 of 1997, FaultMaxx will be priced at $25,000, and TestMaxx at $60,000. The Opmaxx family of products can be purchased as a package for $135,000. The software is currently available for Sun SPARC and Hewlett-Packard HP-PA workstations. Support for Windows NT workstations will be available in Q3 of 1997. Opmaxx Inc., Beaverton, OR. Contact (503) 520-9200 or www.opmaxx.com.

In-system programmable interconnect Lattice Semiconductor announced a high-performance, in-system programmable Generic Digital Crosspoint (ispGDX) logic family consisting of four members: 64, 80, 120, and 160 programmable I/Os. Optimized for digital signal interface and routing applications, this new in-system programmable (ISP) logic architecture features a series of special-purpose programmable I/O cells interconnected by an E2CMOS global routing pool (GRP). The ispGDX devices feature very fast operation, with input-to-output signal delays (Tpd) of 5 ns, clock-to-output delays (Tgco) of 5 ns, and operating frequencies (Fmax) of 111 MHz. The devices will be offered in PLCC, TQFP, and PQFP packages, and all feature IEEE 1149.1-compliant Boundary Scan Test and PCI-compatible outputs. The ispGDX family is supported by Lattice's ispGDX Development System v1.0. The ispGDX software runs on Windows 3.x, 95, and NT, and includes language-based design, a Design Manager GUI, on-line help, and interfaces to third-party timing simulators. The ispGDX development system software is included with all ispDS+ Fitter software at no charge. The ispGDX 160 is sampling now in the 208-pin PQFP package with full production scheduled for later this quarter. Other members of the family will be released during the second half of 1997. The ispGDX160-5Q208 is priced at $27.00 and the ispGDX160-7Q208 is priced at $18.00 in 1,000-piece quantities. Lattice Semiconductor Corp., Hillsboro, OR. Contact (503) 681-0118 or www.latticesemi.com.

New ASIC families VLSI Technology released details of two new deep submicron process technologies. The two processes, VSC9 for 2.5 V operation, and VSC10 for 1.8 V operation, share a fully contacted metal pitch of 0.85 µm and 3.3 V comparable I/O. The two processes also share 35-ps inverter stage delays, as measured in ring oscillators. Although the two processes have different l(eff) gate lengths, they have identical packing densities of up to 40-kgates per mm ² . The parts gain their density through shallow trench isolation and chemical-mechanical polishing as well as the aggressive metal pitches for all five layers of interconnect. In conjunction with the new processes, the company has released new High-Density Initiative (HDI) core and pad libraries. The libraries provide selectable drive strengths for all elements as well as a full complement of I/Os, including TTL, PCI, GTL, GTL+, GTL++, USB, HSTL, LVDS, and PECL. Memories include single-port, dual-port SRAM, and both diffusion and via programmable ROM. The company has also developed a wide range of high-performance packaging to hold the high-density die. VLSI Technology Inc., San Jose, CA. Contact (408) 434-3000 or www.vlsi.com.

Parameter extraction tool BTA Technology announced BSIMPro 4.0, the latest release of the Spice parameter extraction software that supports BSIM3v3.1, a widely used deep submicron MOSFET model developed by University of California at Berkeley. Besides the DC model parameter extraction enhancement, BSIMPro 4.0 supports BSIM3v3.1 AC model, diode model and substrate current model parameters optimization and simulation. To increase device engineers' productivity, BSIMPro 4.0 also provides an automatic model binning routine to allow user to take advantage of the binning option of BSIM3v3. BTA Technology Inc., Santa Clara, CA. Contact (408) 986-1011 or www.btat.com.

Design-space explorer Escalade introduced a new tool that automates the design space exploration process. Design Explorer is an option to Escalade's DesignBook tool that automatically performs numerous module-level synthesis iterations to reach the desired area versus speed tradeoffs for design. Design Explorer provides a new level for design space exploration with the following functions: design configuration for exploration; HDL generation, constraint packing and execution script; and results extraction and visualization. Design Explorer runs on Windows and Unix platforms. The single copy price for the Windows version starts at $5,000. The starting price for a single copy Unix version is $7,500. Escalade Corp., Santa Clara, CA. Contact (408) 654-1600 or www.escalade.com.

PC design environment GateField, a provider of reprogrammable ASIC solutions, and Exemplar Logic, a provider of logic synthesis software, announced that GateField's ProASIC libraries are now available for Examplar's Leonardo logic synthesis environment. This is GateField's first PC-based design environment. Libraries for Leonardo are available immediately. GateField, a division of Zycad Corp., Fremont, CA. Contact (800) 818-5052, (510) 249-5757, gfinfo@gatefield.com, or www.gatefield.com.

EEPROM programmable logic devices Altera unveiled plans for the next generation of its industry-standard MAX programmable logic device families. Dubbed Michelangelo, these devices will range from 32 to 1,008 macrocells, operate at 3.3 V, and offer in-system programming (ISP) at all densities. The Michelangelo product family will be available in a number of package options, including PLCC, PGA, QFP, and SuperBGA packages. Pin counts will range from 44 to 596 pins. Altera plans to release the Michelangelo products in the first half of 1998. Michelangelo products will be supported by Altera's MAX+PLUS II development system. Altera Corp., San Jose, CA. Contact (408) 894-7000 or www.altera.com.

integrated system design  June 1997