TOOLS AND TECHNOLOGIES

Products and services for system design

Synthesis Synopsys unveiled Synopsys 97, a suite of product and technology enhancements to the Design Compiler product family. Synopsys 97, which includes more than 100 enhancements to over 20 products, features timing improvements for high-performance design and new area optimization techniques for cost-sensitive applications. Other new features include gate optimization and timing prediction technology, plus 3-D delay models for improved high-speed performance. In other areas, Synopsys introduced ECO Compiler, a tool for automatically synthesizing ECOs into designs that have already been fully synthesized, placed, and routed. By reusing almost all of the previous version of a design, ECO Compiler enables designers to implement late arriving functional changes very quickly. ECO Compiler works with Design Compiler. Pricing for Synopsys 97 depends on configuration. Pricing for ECO Compiler starts at $100,000. Synopsys Inc., Mountain View, CA. Contact (415) 962-5000 or www. Synopsys .com.

Verilog debugging tools Novas Software announced Debussy 3.0, a complete Verilog HDL debugging environment. An important element of Debussy, the waveform viewer, has been in use for two years under OEM relationships. Debussy adds viewing, analysis, and debugging features to existing Verilog HDL environments. It provides transparent access to large, multi-directory source trees, with full design tracing. The HDL hierarchy can be displayed as module trees, source code, and schematics. All three modes interact with each other through drag-and-drop. Post-synthesis gate-level HDL can also be correlated against its presynthesis source. The product has a synchronized window feature, allowing multiple simulations to be viewed simultaneously to reveal synthesis, timing, and analog problems. Automatic backannotation displays bus and signal values on the schematics in step with the simulation windows. Debussy is compatible with most Verilog HDL and simulator environments. The complete Debussy environment starts at $8,000. Novas Software, Campbell, CA. Contact info@novassoft.com or www.novassoft.com.

Verilog interfaces Summit Design enhanced the integration of its Visual HDL graphical design entry environment with Verilog functional design verification tools. Visual HDL now includes a Verilog interface to Quickturn's HDL-ICE in-circuit RTL emulation software and supports graphical simulation with Viewlogic 's VCS. Visual HDL's interface with VCS supports graphical entry of Verilog code with block diagrams, flow charts, algorithmic state machines, state diagrams, truth tables, gate-level schematics, and libraries of parameterized modules. Visual HDL users can target the graphical entry tool's RTL output directly for emulation by Quickturn. Visual HDL includes a new control window for HDL-ICE that improves the user interface. Using the scripting capabilities of Quickturn Emulation Language, users also can encapsulate HDL-ICE and key emulation scripts within the Visual HDL graphical environment. Summit's VCS simulation and HDL-ICE RTL emulation interfaces for Verilog-based Visual HDL users are available immediately. The HDL-ICE interface is free, and the VCS interface for Unix workstations is priced at $6,000. Summit Design Inc., Beaverton, OR. Contact (800) 661-4333 or www.summit-design.com.

VHDL synthesis Minc introduced VHDL Easy, a new synthesis product operating on Windows 95 and NT platforms. The VHDL Easy synthesizer is a VHDL-based logic synthesizer with a simplified user interface and preprogrammed, but modifiable, synthesis to eliminate many of the obstacles in programmable logic design. Users can choose from fitters for Actel, Altera, AMD, Lattice, and Xilinx devices, with other devices to be added in the future. As a part of the introduction of VHDL Easy, a full featured tutorial on VHDL is included with the software. Introductory pricing is $495. Minc Inc., Boulder, CO. Contact (719) 590-1155, info@minc.com, or www.minc.com.

Support for Xilinx XC4000EX family Exemplar Logic and Xilinx announced that Exemplar's Leonardo synthesis solution is fully certified for the Xilinx XC4000EX family, with unique support for the family's Select-RAM memory feature. Exemplar's Galileo design environment will support the Xilinx XC4000EX family in late Q2. Leonardo also supports Xilinx' XC3000, XC4000, XC4000E, XC5200, XC7000, and XC9500 families. Support for the XC4000EX is available now with Leonardo version 4.03. Prices for Leonardo start at $14,990. Galileo will support the XC4000EX with version 4.1 late in the second quarter of 1997. Prices for Galileo start at $7,500. Exemplar Logic Inc., Alameda, CA. Contact (510) 337-3700, info@exemplar.com, or www.exemplar.com.

Embedded memories Artisan Components, formerly VLSI Libraries Inc., introduced a new family of 0.25-µm memory generators. By utilizing patented design techniques and by tuning the product for each customer's 0.25-µm process, Artisan Components' new memory generators can create a variety of embedded memories that can operate at system speeds in excess of 300 MHz (worst case, 64 kbits; 500 MHz under "typical" process conditions). The company also announced that these products include the company's new universal test interface (UTI), which enables the memories to support all standard test methodologies, including multiplexed-isolation, scan, serial test, parallel BIST, and scan-BIST. The 300-MHz Process-Perfect memory generator family includes a dual-port SRAM generator, a high-speed dual-port register file generator, and a high-speed three-port register file generator. The generators create all standard EDA tool views. All memory generators are available today. Pricing will be announced at a later date. Artisan Components Inc., San Jose, CA. Contact (408) 453-1000, info@artisan.com, or www.artisan.com.

RTL formal verification Chrysalis Symbolic Design announced the Multi-Cycle Analyzer (MCA) module for its Design Insight formal RTL design verification product family. Design Insight is used by ASIC and IC engineers to validate the functionality of RTL design specifications. The new module extends Design Insight's capabilities by adding a symbolic simulator that lets designers analyze and prove the correct operation of complex protocol details over many clock cycles. It supports both standard Verilog change dump (VCD) and binary textual vector formats for input and output. Design Insight uses the language-neutral Chrysalis software architecture to compile users' register-transfer-, gate-, and switch-level descriptions, including standard simulation libraries, into a unique symbolic logic representation. Designers then use the compiled symbolic logic database to apply model-checking proofs and interactively explore the operation of a design. The same compiled representation is used with Chrysalis' Design VERIFYer formal equivalence-checking software. Chrysalis Symbolic Design Inc., North Billerica, MA. Contact: (508) 475-7700 www@chrysalis.com.

Memory models Denali Software has implemented the Open Model Interface (OMI) linking modeling and verification environments. OMI is the standard interface specification from the Open Modeling Foundation (OMF) to enable interoperability of models and their secure distribution across verification platforms. It comes standard with Denali Software's Memory Modeler, offering a seamless and transparent link between the company's modeling environment and a number of verification environments. Memory Modeler, introduced last year, allows designers to create models or cores for new memory components or reuse existing intellectual property (IP). Designers characterize features, timing, and manufacturing of memory parts using an interactive fill-in-the-form interface. Interactive debugging and testbench support features help accelerate debugging and regression testing, and simulation and analysis features extend the simulation environment. Available object-oriented models range from DRAM, SRAM, and SSRAM to flash, PROM, and FIFO. Memory Modeler starts at $5,000 and is available now for SunOS, Solaris, and HP-UX operating systems. Denali Software Inc., Palo Alto, CA. Contact (415) 325-7241, sanjay@denalisoft.com, or www.denalisoft.com.

CPLDs Vantis, AMD's programmable logic subsidiary, announced it has scaled its Mach 4 family to a 0.35-µm EEPROM process and extended its offerings with the addition of four Mach 4 devices in both 3.3- and 5-V versions. The new devices incorporate Vantis' SpeedLocking feature, which provides fast performance regardless of product term loading or interconnect routing. The four devices are the M4-192/96, a 192-macrocell device with 96 I/Os; the M4-64/32, a 64-macrocell device with 32 I/Os; the M4-96/48, a 96-macrocell device with 48 I/Os; and the M4-32/32, a 32-macrocell device with 32 I/Os. In addition, Vantis announced the availability of 10-ns versions of its M4-128/64 and M4-256/128 macrocell products and price reductions of up to 32 percent on existing 12- and 15-ns versions of the M4-128 and M4-256 devices. The 10-ns M4-256 and M4-128 devices are available now through Vantis' distribution channel and are priced at $86.87 and $28.20, respectively, in 1000-piece quantities. Members of the family come in a PLCC (M4-64, M4-32), PQFP (M4-96, M4-128, M4-192, M4-256), or TQFP (M4-32, M4-64, M4-96, M4-128). Vantis Corp., Sunnyvale, CA. Contact (888) VANTIS2 or www.vantis.com.

Power analysis software The latest release of Sente's power analysis software suite for IC design supports VHDL. Sente's Watt Watcher allows IC designers to use a single power estimation toolset throughout the entire design. Watt Watcher accepts model data at many levels of abstraction, from gate primitives to memories, megacells, and cores, so that designers can estimate power on small modules or the entire chip. In addition, Watt Watcher's Delta Propagation techniques permit the designer to monitor the effect of small changes in activity on circuit performance and to analyze circuits for their sensitivity to various input activities. During a design's early stages, Watt Watcher/Architect works at the register transfer level to get early power estimates on architectural power dissipation characteristics before synthesis. After synthesis, designers use Watt Watcher/Gate, a gate-level simulator, to estimate power at the gate level. Release 2.3 includes support for a variety of VHDL and Verilog simulators. The Watt Watcher product family includes a GUI, the Watt Watcher engine, and a language parser for Verilog HDL and VHDL. Each module is sold separately. The VHDL module, like the Verilog HDL module, is priced at $15,000. The Watt Watcher engine is priced at under $60,000. Watt Watcher is available on Sun workstations running under either Solaris or SunOS and on Hewlett-Packard workstations running under HP-UX. Sente Inc., Chelmsford, MA. Contact (508) 244-1100, ext. 311, sente@powereda.com, or www.powereda.com.

Larger PLDs Altera Corp. (San Jose, CA) announced the shipment of the EPF10K130V. Using a 3.3-V, 0.35-µm process, the device targets customers' demand for ever-larger programmable logic devices. Altera's patented embedded array architecture allows for the implementation of random logic and also provides embedded array blocks (EABs), which can implement a variety of memory and specialized logic functions as efficiently as embedded gate arrays. The EPF10K130V, containing 6,656 logic elements and 32 kbits of on-chip RAM, is the second member of the 3.3-V Flex 10KA family to ship. The EPF10K130V's architecture features efficient EABs which may be used as RAM, ROM, FIFO, and dual-port SRAM. In addition, the EABs can be used for specialized logic functions such as multipliers, ALUs, or DSP functions. The logic array blocks (LABs) perform all general-purpose logic functions.

The EPF10K130V offers the MultiVolt interface to enable the device to interface with 5- and 3.3-V devices and can implement designs containing 82 to 211 kgates of logic and RAM. It is supported by Altera's Max+Plus II development system for PC and workstation platforms. The EPF10K130V is available now in a 599-pin PGA, priced at $895 in quantities of 100. In the second half of 1997, it is scheduled to be available in a 600-pin BGA. *In lots of 5,000, the EPF10K130V in a 600-pin BGA is projected to sell for $275 at the end of 1997. Altera Corp., San Jose, CA. Contact (408) 894-7000 www.altera.com.

High-level design automation Escalade began shipping the latest release of DesignBook, created to help designers use a high-level design automation (HLDA) methodology. DesignBook version 3.0 adds a host of features, including full support for hardware description languages, language-independent design capture and representation, and the ability to manage data elements and import existing HDL designs. In addition, DesignBook has added support for the most popular logic simulators. Cross-language identifier checking warns of potential problems during language re-targeting. Block diagram generation from VHDL and Verilog, free of data flow restrictions, accelerates the migration process. DesignBook Version 3.0 is available in volume shipments today, running on Windows, Sun, and Hewlett-Packard platforms. The single-copy U.S. pricing for the Windows version starts at $20,000. The single-copy Unix version is priced from $30,000. Escalade Corp., Santa Clara, CA. Contact (408) 654-1600 or www.escalade.com.

Work group management tools Synchronicity launched DesignSync HLD, the first in a series of design management groupware (DMG) that allows true collaborative design on the Internet and World Wide Web for engineering work groups using EDA software. DesignSync HLD uses a secure, Web-based client/server architecture that includes configuration management with revision/release control and check-in and -out of files and releases. Initially supporting designers using VHDL and Verilog HDL, it includes a menu-driven graphical user interface that lets designers view the design data hierarchy on a project intranet server, either locally or remotely over the Internet. A functionally equivalent command-line interface is also available, adding the flexibility of the TCL extension language. Communications and transactions between client and server are fully secure as a result of prerequisite user authentication and strong data encryption. DesignSync HLD, to be shipped starting in the third quarter, runs on either Unix or Windows 95 and Windows NT 4.0 platforms. It is priced from $25,000 for a five-client configuration. Synchronicity Inc., Boston, MA. Contact (510) 462-4993, mark@syncinc.com, or www.syncinc.com.

Internet EDA Viewlogic introduced Design Exchange to provide engineering product development teams with design data management and component management and to promote design collaboration. Design Exchange combines electronic design automation, information technology, and Internet/intranet-based communications, providing a secure design collaboration environment for geographically dispersed design teams. It includes two new servers and several Web browser plug-ins. The servers are DxDataBook, which is used for component selection and verification, and DxDataManager, for design data management and reuse. With their Web browsers, design engineers can use DxDataBook to search for component information from their desktop. Design Exchange clients, plug-ins, and Web server extensions will be distributed with the purchase of a server configuration. Experienced technical consultants are available to provide integration assistance and complete integration services to help customers integrate Design Exchange into their existing methodology. Viewlogic Systems Inc., Marlboro, MA. Contact (508) 480-0881 or www.viewlogic.com.

Hardware/software co-verification Mentor Graphics announced a new release of its hardware/software co-verification product, Seamless Co-Verification Environment (CVE). The enhanced Seamless CVE 2.0 includes a method for inserting Seamless CVE into design flows, reducing memory modeling time. The new release adds support for additional microprocessors, as well as Cadence's Leapfrog simulator. Mentor has teamed with Denali Software Inc. (Palo Alto, CA) to speed up the insertion of Seamless CVE's high-performance memory models into existing design flows. Seamless CVE Processor Support Packages (PSPs) now include the ARM7, Intel 960, Motorola 680xx, Motorola 683xx, Motorola ColdFire, and Motorola PowerPC families of processors, with beta support for the Intel x86 and Motorola MPC860. Seamless CVE 2.0 is available for $75,000 (floating) on SunOS, Sun Solaris, and HP-PA platforms. PSPs start at $20,000 (floating). Seamless CVE is available from Mentor's Co-Design Web site, CD, or tape. Internet distribution is subject to the local laws and customs of each country. Mentor Graphics Corp., Wilsonville, OR. Contact www.mentorg.com or www.mentorg.com/codesign.

ASICs with DRAM Samsung Semiconductor announced a deep submicron ASIC family based on its 0.35-µm process technology. The new family is simultaneously available in cell-based (STD90), gate array (KG90), customer-owned tooling (COT), and merged DRAM and logic (MDL90) options. The cell-based ASICs offer more than 2 million gates of random logic, and the MDL ASICs allow designers to embed up to 24 Mbits of single-transistor EDO DRAM or SDRAM. The family also provides a broad offering of processor cores and I/O and analog blocks, as well as a comprehensive library of digital macrocells. Using Samsung's deep submicron ASIC architecture, which is based on three- and four- layer metal with three- layer polysilicon/titanium salicide on the source and drain, the new ASICs achieve a density of up to 18 raw kgates per square millimeter. Pricing depends on design specifications, architecture, complexity of design, package type, and customer required services. NRE charges begin at $100,000. Samsung Semiconductor Inc., San Jose, CA. Contact (800) 446-2760 or (408) 954-7000.

Gate arrays NEC Electronics Inc. announced a new family of 0.35-µm-drawn gate arrays. The CMOS-9HD high-density gate arrays will assist ASIC customers with improved turnaround time, lower non-recurring engineering (NRE) and manufacturing costs, and reduced power dissipation. They are the first available products based on a new ASIC architecture called the NXT, developed by In-Chip Systems (Los Altos, CA), a startup company specializing in system ASIC design technologies. The family uses NEC's three- layer-metal 0.35-µm process technology. With the coupling of the channeless 3.3-V NXT architecture, these products have more than twice the density of the company's previous 0.35-µm gate arrays. The family includes nine masters that support 58,000 to 1.5 million gates and can be used in applications requiring system speeds of up to 155 MHz. The CMOS-9HD supports all standard I/O and macro functions. Pricing depends on design specifications, complexity, and package type. NEC Electronics Inc., Santa Clara, CA. Contact (800) 366-9782 or www.nec.com.

integrated system design  July 1997